CPU 1 CPU 2 CPU 3
mremap(old_addr, new_addr) page_shrinker/try_to_unmap_one
mmap_write_lock_killable()
addr = old_addr
lock(pte_ptl)
lock(pud_ptl)
pud = *old_pud
pud_c
CPU 1 CPU 2 CPU 3
mremap(old_addr, new_addr) page_shrinker/try_to_unmap_one
mmap_write_lock_killable()
addr = old_addr
lock(pte_ptl)
lock(pmd_ptl)
pmd = *old_pmd
pmd_c
Linus Torvalds writes:
> On Mon, May 24, 2021 at 3:38 AM Aneesh Kumar K.V
> wrote:
>>
>> Avoid the above race with MOVE_PMD by holding pte ptl in mremap and waiting
>> for
>> parallel pagetable walk to finish operating on pte before updating new_pmd
>
> Ack on the concept.
Should we worry abo
On 24/05/21 21:48, Srikar Dronamraju wrote:
> * Valentin Schneider [2021-05-24 15:16:09]:
>> Ok so from your arch you can figure out the *size* of the set of unique
>> distances, but not the individual node_distance(a, b)... That's quite
>> unfortunate.
>
> Yes, thats true.
>
>>
>> I suppose one w
* Valentin Schneider [2021-05-25 11:21:02]:
> On 24/05/21 21:48, Srikar Dronamraju wrote:
> > * Valentin Schneider [2021-05-24 15:16:09]:
> >> Ok so from your arch you can figure out the *size* of the set of unique
> >> distances, but not the individual node_distance(a, b)... That's quite
> >> u
Patch adds performance stats reporting support for nvdimm.
Added interface includes support for pmu register/unregister
functions. A structure is added called nvdimm_pmu to be used for
adding arch/platform specific data such as supported events and pmu
event functions like event_init/add/read/del.
Patch adds support for performance monitoring of papr-scm
nvdimm devices via perf interface. It adds pmu functions
like add/del/read/event_init for nvdimm_pmu struture.
Patch adds a new parameter 'priv' in pdev_archdata structure to save
nvdimm_pmu device pointer, to handle the unregistering of pm
This patch add event format and events details in ABI
documentation
Signed-off-by: Kajol Jain
---
Documentation/ABI/testing/sysfs-bus-papr-pmem | 25 +++
1 file changed, 25 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-papr-pmem
b/Documentation/ABI/testing/sysf
Patch adds performance stats reporting support for nvdimm.
Added interface includes support for pmu register/unregister
functions. A structure is added called nvdimm_pmu to be used for
adding arch/platform specific data such as supported events and pmu
event functions like event_init/add/read/del.
Patch here adds cpu hotplug functions to nvdimm pmu.
It adds cpumask to designate a cpu to make HCALL to
collect the counter data for the nvdimm device and
update ABI documentation accordingly.
Result in power9 lpar system:
command:# cat /sys/devices/nmem0/cpumask
0
Signed-off-by: Kajol Jain
---
The "no_handler_test" in ebb selftests attempts to read the PMU
registers after closing of the event via helper function
"dump_ebb_state". With the MMCR0 control bit (PMCCEXT) in ISA v3.1,
read access to group B registers is restricted when MMCR0 PMCC=0b00.
Hence the call to dump_ebb_state after cl
The "no_handler_test" in ebb selftests attempts to read the PMU
registers twice via helper function "dump_ebb_state". First dump is
just before closing of event and the second invocation is done after
closing of the event. The original intention of second
dump_ebb_state was to dump the state of reg
With the MMCR0 control bit (PMCCEXT) in ISA v3.1, read access to
group B registers is restricted when MMCR0 PMCC=0b00. In other
platforms (like power9), the older behaviour works where group B
PMU SPRs are readable.
Patch creates a selftest which verifies that the test takes a
SIGILL when attempti
Linus Torvalds writes:
> On Sun, May 23, 2021 at 11:04 PM Aneesh Kumar K.V
> wrote:
>>
>> Add new helper flush_pte_tlb_pwc_range() which invalidates both TLB and
>> page walk cache where TLB entries are mapped with page size PAGE_SIZE.
>
> So I dislike this patch for two reasons:
>
> (a) naming
The "no_handler_test" in ebb selftests attempts to read the PMU
registers after closing of the event via helper function
"dump_ebb_state". With the MMCR0 control bit (PMCCEXT) in ISA v3.1,
read access to group B registers is restricted when MMCR0 PMCC=0b00.
Hence the call to dump_ebb_state after cl
The "no_handler_test" in ebb selftests attempts to read the PMU
registers twice via helper function "dump_ebb_state". First dump is
just before closing of event and the second invocation is done after
closing of the event. The original intention of second
dump_ebb_state was to dump the state of reg
With the MMCR0 control bit (PMCCEXT) in ISA v3.1, read access to
group B registers is restricted when MMCR0 PMCC=0b00. In other
platforms (like power9), the older behaviour works where group B
PMU SPRs are readable.
Patch creates a selftest which verifies that the test takes a
SIGILL when attempti
On Tue, May 25, 2021 at 06:52:16PM +0530, Kajol Jain wrote:
> Patch here adds cpu hotplug functions to nvdimm pmu.
I'm thinking "Patch here" qualifies for "This patch", see
Documentation/process/submitting-patches.rst .
> It adds cpumask to designate a cpu to make HCALL to
> collect the counter d
On Tue, May 25, 2021 at 12:07:23PM +0530, Kajol Jain wrote:
> Fixed the eventcode values in the power10 json event files to append
> "0x" since these are hexadecimal values.
> Patch also changes event description of PM_EXEC_STALL_LOAD_FINISH and
> PM_EXEC_STALL_NTC_FLUSH event and move some events
On Tue, May 25, 2021 at 09:42:15AM -0500, Paul A. Clarke wrote:
> On Tue, May 25, 2021 at 12:07:23PM +0530, Kajol Jain wrote:
> > Fixed the eventcode values in the power10 json event files to append
> > "0x" since these are hexadecimal values.
> > Patch also changes event description of PM_EXEC_STA
On Tue, May 25, 2021 at 3:28 AM Aneesh Kumar K.V
wrote:
>
> How about flush_tlb_and_page_table_cache() ?
Honestly, I'd prefer it to be a separate function.
So keep the existing
flush_tlb()
as-is, and add a
flush_tlb_walking_cache()
and document that any architecture that flushes
On Mon, May 24, 2021 at 10:44 PM A lneesh Kumar K.V
wrote:
>
> Should we worry about the below race. The window would be small
>
> CPU 1 CPU 2 CPU 3
>
> mremap(old_addr, new_addr) page_shrinker/try_to_unmap_one
>
> mmap_write_lock_ki
On Mon, May 24, 2021 at 10:34 PM Aneesh Kumar K.V
wrote:
>
> @@ -221,6 +222,9 @@ static inline void page_vma_mapped_walk_done(struct
> page_vma_mapped_walk *pvmw)
> spin_unlock(pvmw->pte_ptl);
> if (pvmw->pmd_ptl)
> spin_unlock(pvmw->pmd_ptl);
> + if
> For those reading along the v2 mentioned in that thread was posted as
> https://lore.kernel.org/linux-i2c/20170511122033.22471-1-joakim.tjernl...@infinera.com/
>
> there was a bit of discussion but it seemed to die out without reaching
> a conclusion.
>
> The i2c-mpc driver is now using the
On Wed, May 12, 2021 at 09:20:48AM +1200, Chris Packham wrote:
> The P2040/P2041 has an erratum where the i2c recovery scheme
> documented in the reference manual (and currently implemented
> in the i2c-mpc.c driver) does not work. The errata document
> provides an alternative that does work. This
Tested patch with the following steps:
1. Extracted all the 244 events from the patch.
2. Check them in 'perf list' - all 244 events found
3. Ran all the events with 'perf stat -e "event name" sleep 1', all ran fine.
No errors were seen in 'dmesg'
Tested-by: Nageswara R Sastry
> On 25-May
On Fri, 21 May 2021 at 07:51, Christoph Hellwig wrote:
>
> Hi all,
>
> this series is the first part of cleaning up lifetimes and allocation of
> the gendisk and request_queue structure. It adds a new interface to
> allocate the disk and queue together for bio based drivers, and a helper
> for cl
Chris Packham writes:
> The i2c controllers on the P2040/P2041 have an erratum where the
> documented scheme for i2c bus recovery will not work (A-004447). A
> different mechanism is needed which is documented in the P2040 Chip
> Errata Rev Q (latest available at the time of writing).
>
> Signed-o
Chris Packham writes:
> The i2c controllers on the P1010 have an erratum where the documented
> scheme for i2c bus recovery will not work (A-004447). A different
> mechanism is needed which is documented in the P1010 Chip Errata Rev L.
>
> Signed-off-by: Chris Packham
> ---
>
> Notes:
> Chang
Wolfram Sang writes:
> On Wed, May 12, 2021 at 09:20:48AM +1200, Chris Packham wrote:
>> The P2040/P2041 has an erratum where the i2c recovery scheme
>> documented in the reference manual (and currently implemented
>> in the i2c-mpc.c driver) does not work. The errata document
>> provides an alter
defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a001-20210525
i386
defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a001-20210525
allyesconfig
mips allmodconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a001-20210525
i386 randconfig-a002-20210525
i386 randconfig-a005-20210525
i386
On Wed, May 26, 2021 at 12:41:37AM +0200, Ulf Hansson wrote:
> On Fri, 21 May 2021 at 07:51, Christoph Hellwig wrote:
> >
> > Hi all,
> >
> > this series is the first part of cleaning up lifetimes and allocation of
> > the gendisk and request_queue structure. It adds a new interface to
> > alloca
> On 25-May-2021, at 8:57 PM, Paul A. Clarke wrote:
>>
> I lost the original message, but Nageswara Sastry said:
>> 1. Extracted all the 244 events from the patch.
>> 2. Check them in 'perf list' - all 244 events found
>> 3. Ran all the events with 'perf stat -e "event name" sleep 1', all ran
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