Suka,
Please CC Christophe who as an alternative way of doing this. We ned to get
agreement across all users of TIDR/AS_notify...
His patch is here:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-August/161582.html
Mikey
On Tue, 2017-08-29 at 19:38 -0700, Sukadev Bhattiprolu wrote:
> We
On Tue, 2017-08-29 at 20:56 -0400, Jerome Glisse wrote:
> On Tue, Aug 29, 2017 at 05:11:24PM -0700, Linus Torvalds wrote:
>
> > People - *especially* the people who saw issues under KVM - can you
> > try out Jérôme's patch-series? I aded some people to the cc, the full
> > series is on lkml. Jérôm
On 27/08/2017 02:18, Kirill A. Shutemov wrote:
> On Fri, Aug 18, 2017 at 12:05:13AM +0200, Laurent Dufour wrote:
>> +/*
>> + * vm_normal_page() adds some processing which should be done while
>> + * hodling the mmap_sem.
>> + */
>> +int handle_speculative_fault(struct mm_struct *mm, unsigned long a
Geert Uytterhoeven writes:
> Signed-off-by: Geert Uytterhoeven
> Acked-by: Rob Herring
> ---
Rob this has your ack, but I'd expect it to go via your tree? Or should
I grab it?
cheers
> diff --git a/Documentation/devicetree/booting-without-of.txt
> b/Documentation/devicetree/booting-without-
On 30/08/2017 07:58, Peter Zijlstra wrote:
> On Wed, Aug 30, 2017 at 10:33:50AM +0530, Anshuman Khandual wrote:
>> diff --git a/mm/filemap.c b/mm/filemap.c
>> index a497024..08f3042 100644
>> --- a/mm/filemap.c
>> +++ b/mm/filemap.c
>> @@ -1181,6 +1181,18 @@ int __lock_page_killable(struct page *__
On 30/08/2017 07:03, Anshuman Khandual wrote:
> On 08/29/2017 07:15 PM, Peter Zijlstra wrote:
>> On Tue, Aug 29, 2017 at 03:18:25PM +0200, Laurent Dufour wrote:
>>> On 29/08/2017 14:04, Peter Zijlstra wrote:
On Tue, Aug 29, 2017 at 09:59:30AM +0200, Laurent Dufour wrote:
> On 27/08/2017 02
On Tue, Aug 29, 2017 at 07:18:01PM -0300, Jose Ricardo Ziviani wrote:
> Hello!
>
> This patch implements MMIO emulation for two instructions: lvx and stvx. I
> started to implement other instructions but I'd like to have this reviewed
> beforehand because this is my first patch here and I'll cer
With the optimizations introduced by commit a46cc7a90fd8
("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no
longer flushes the page walk cache with radix. This patch introduces
flush_all_mm(), which flushes everything, tlb and pwc, for a given mm.
Signed-off-by: Frederic Barrat
---
cxl keeps a driver use count, which is used with the hash memory model
on p8 to know when to upgrade local TLBIs to global and to trigger
callbacks to manage the MMU for PSL8.
If a process opens a context and closes without attaching or fails the
attachment, the driver use count is never decrement
The PSL and nMMU need to see all TLB invalidations for the memory
contexts used on the adapter. For the hash memory model, it is done by
making all TLBIs global as soon as the cxl driver is in use. For
radix, we need something similar, but we can refine and only convert
to global the invalidations
Currently these tests won't build with a `--enable-default-pie`
compiler as they require r30 to be clobbered. This gives
an error:
ptrace-tm-spd-gpr.c:41:2: error: PIC register clobbered by 'r30' in 'asm'
This forces these tests to be built no-pie.
Signed-off-by: Michael Neuling
---
tools/tes
"Guilherme G. Piccoli" writes:
> On 08/29/2017 08:22 AM, Michael Ellerman wrote:
>> "Guilherme G. Piccoli" writes:
>>
>>> On 08/28/2017 02:56 AM, Michael Ellerman wrote:
Some Power9 boxes will have this adapter installed, so add it to the
defconfig so we can boot on those machines wit
Nicholas Piggin writes:
> When stop is executed with EC=ESL=0, it appears to execute like a
> normal instruction (resuming from NIP when woken by interrupt).
> So all the save/restore handling can be avoided completely. In
> particular NV GPRs do not have to be saved, and MSR does not have
> to b
Hi Mpe,
Thanks for reviewing the patch
Michael Ellerman writes:
>> +ctx->elem->software_state = cpu_to_be32(CXL_PE_SOFTWARE_STATE_V);
>> +/* Make sure the changes to the PE are visible to the card */
>
> A barrier orders something vs something else. So what's the something
> else in thi
On Wed, 30 Aug 2017 21:25:59 +1000
Michael Ellerman wrote:
> Nicholas Piggin writes:
>
> > When stop is executed with EC=ESL=0, it appears to execute like a
> > normal instruction (resuming from NIP when woken by interrupt).
> > So all the save/restore handling can be avoided completely. In
> >
Vaibhav Jain writes:
> Hi Mpe,
>
> Thanks for reviewing the patch
>
> Michael Ellerman writes:
>
>>> + ctx->elem->software_state = cpu_to_be32(CXL_PE_SOFTWARE_STATE_V);
>>> + /* Make sure the changes to the PE are visible to the card */
>>
>> A barrier orders something vs something else. So
On 08/30/2017 08:07 AM, Michael Ellerman wrote:
>[...]
> OK. So maybe when the petitboot kernel moves up to 4.14 they may want to
> flip it back to being a module.
>
OK, I'll be tuned! Thanks
> I think the majority of machines that have one of these adapters will be
> using it for their root di
Frederic Barrat writes:
> With the optimizations introduced by commit a46cc7a90fd8
> ("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no
> longer flushes the page walk cache with radix. This patch introduces
> flush_all_mm(), which flushes everything, tlb and pwc, for a given mm.
>
>
Frederic Barrat writes:
> cxl keeps a driver use count, which is used with the hash memory model
> on p8 to know when to upgrade local TLBIs to global and to trigger
> callbacks to manage the MMU for PSL8.
>
> If a process opens a context and closes without attaching or fails the
> attachment, th
Hi Dave,
Thank you for acking.
The reason I am not doing initializing stores is because they require a
membar, even if only regular stores are following (I hoped to do a
membar before first load). This is something I was thinking was not
true, but after consulting with colleagues and checking
I'm dropping this series, as there was a recent change done in the
memory context that I can reuse.
The follow up of the story is:
http://patchwork.ozlabs.org/patch/807570/
Fred
Le 02/08/2017 à 22:29, Frederic Barrat a écrit :
capi2 and opencapi require the TLB invalidations being sent for
From: Balbir Singh
> Sent: 30 August 2017 01:28
> ISA 300 defines hypervisor decrementer to be 64 bits in length.
> This patch extends the print format for all archs to be 64 bits
>
> Signed-off-by: Balbir Singh
> ---
> arch/powerpc/xmon/xmon.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletio
Le 30/08/2017 à 15:17, Michael Ellerman a écrit :
Frederic Barrat writes:
With the optimizations introduced by commit a46cc7a90fd8
("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no
longer flushes the page walk cache with radix. This patch introduces
flush_all_mm(), which flush
On 08/29/2017 09:35 PM, Michael Ellerman wrote:
> John Allen writes:
>
>> Check if an LMB is assigned before attempting to call dlpar_acquire_drc in
>> order to avoid any unnecessary rtas calls. This substantially reduces the
>> running time of memory hot add on lpars with large amounts of memory
On 08/30/2017 01:09 AM, Michael Ellerman wrote:
> Daniel Henrique Barboza writes:
>
>> Hi Ben,
>>
>> On 08/29/2017 06:55 PM, Benjamin Herrenschmidt wrote:
>>> On Tue, 2017-08-29 at 17:43 -0300, Daniel Henrique Barboza wrote:
Hi,
This is a scenario I've been facing when working in e
On 08/30/2017 09:35 AM, Nathan Fontenot wrote:
> On 08/29/2017 09:35 PM, Michael Ellerman wrote:
>> John Allen writes:
>>
>>> Check if an LMB is assigned before attempting to call dlpar_acquire_drc in
>>> order to avoid any unnecessary rtas calls. This substantially reduces the
>>> running time of
On Tue, Aug 29, 2017 at 08:56:15PM -0400, Jerome Glisse wrote:
> I will wait for people to test and for result of my own test before
> reposting if need be, otherwise i will post as separate patch.
>
> > But from a _very_ quick read-through this looks fine. But it obviously
> > needs testing.
> >
Hi Boris,
On 08/29/2017 05:22 AM, Borislav Petkov wrote:
[...]
On Mon, Jul 24, 2017 at 02:07:56PM -0500, Brijesh Singh wrote:
Some KVM specific MSR's (steal-time, asyncpf, avic_eio) allocates per-CPU
MSRs
variable at compile time and share its physical address with hype
Hello Wolfram,
On Tue, Aug 29, 2017 at 10:48 AM, Wolfram Sang wrote:
>
>> I don't have a DT based system at hand now, but I'll test it again and
>> let you know probably tomorrow.
>
> I will try again today, too. Thanks!
>
Ok, I had some time to do some tests again. I used an ARM Chromebook
(Exy
platform_suspend_ops are not supposed to change at runtime.
Functions suspend_set_ops working with const platform_suspend_ops.
So mark the non-const structs as const.
Signed-off-by: Arvind Yadav
---
arch/powerpc/sysdev/ppc4xx_cpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
With gcc 7 from Ubuntu 17.10 I'm getting the follwing error building the
ptrace selftests for powerpc:
ptrace-tm-vsx.c: In function ‘tm_vsx’:
ptrace-tm-vsx.c:42:2: error: PIC register clobbered by ‘r2’ in ‘asm’
asm __volatile__(
^~~
make[1]: *** [ptrace-tm-vsx] Error 1
ptrace-tm-sp
On Wed, Aug 30, 2017 at 06:19:02PM +0200, Javier Martinez Canillas wrote:
> Hello Wolfram,
>
> On Tue, Aug 29, 2017 at 10:48 AM, Wolfram Sang wrote:
> >
> >> I don't have a DT based system at hand now, but I'll test it again and
> >> let you know probably tomorrow.
> >
> > I will try again today,
From: Pasha Tatashin
Date: Wed, 30 Aug 2017 09:19:58 -0400
> The reason I am not doing initializing stores is because they require
> a membar, even if only regular stores are following (I hoped to do a
> membar before first load). This is something I was thinking was not
> true, but after consult
On Wed, Aug 30, 2017 at 11:18:42AM -0500, Brijesh Singh wrote:
> I was trying to avoid mixing early and no-early set_memory_decrypted() but if
> feedback is: use early_set_memory_decrypted() only if its required otherwise
> use set_memory_decrypted() then I can improve the logic in next rev. thanks
On Fri, Aug 11, 2017 at 06:19:33PM +1000, Alexey Kardashevskiy wrote:
> From: Gavin Shan
>
> The PowerNV platform is the only user of pcibios_sriov_disable().
> The IOV BAR could be shifted by pci_iov_update_resource(). The
> warning message in the function is printed if the IOV capability
> is i
Having the CPU identifier in the debug logs is helpful when tracking
issues. Also add some more logging and fix a compile issue in
xive_do_source_eoi().
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
xive_poke_esb() is performing a load/read so it is better named as
xive_esb_read() as we will need to introduce a xive_esb_write()
routine. Also use the XIVE_ESB_LOAD_EOI offset when EOI'ing LSI
interrupts.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
Changes since v1:
- fix
The H_INT_ESB hcall() is used to issue a load or store to the ESB page
instead of using the MMIO pages. This can be used as a workaround on
some HW issues. The OS knows that this hcall should be used on an
interrupt source when the ESB hcall flag is set to 1 in the hcall
H_INT_GET_SOURCE_INFO.
To
Hello,
On a POWER9 sPAPR machine, the Client Architecture Support (CAS)
negotiation process determines whether the guest operates with an
interrupt controller using the legacy model, as found on POWER8, or in
XIVE exploitation mode, the newer POWER9 interrupt model. This
patchset is the latest pro
On POWER9, the Client Architecture Support (CAS) negotiation process
determines whether the guest operates in XIVE Legacy compatibility or
in XIVE exploitation mode. Now that we have initial guest support for
the XIVE interrupt controller, let's inform the hypervisor what we can
do.
The platform a
This routine will be used in the spapr backend. Also introduce a short
xive_alloc_order() helper.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/sysdev/xive/common.c| 16
arch/powerpc/sysdev/xive/native.c| 16 +---
arch/po
This is the framework for using XIVE in a PowerVM guest. The support
is very similar to the native one in a much simpler form.
Each source is associated with an Event State Buffer (ESB). This is a
two bit state machine which is used to trigger events. The bits are
named "P" (pending) and "Q" (queu
>
> I think we should talk about the same case: Let me repeat what I did:
>
> 1) I added your patch "eeprom: at24: Add OF device ID table"
> 2) I added an EEPROM node to an I2C
>
> + eeprom@50 {
> + compatible = "renesas,24c01";
> + reg = <0x50>;
> + };
>
> -
It will be required later by the H_INT_ESB hcall.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/xive.h | 1 +
arch/powerpc/sysdev/xive/native.c | 2 ++
arch/powerpc/sysdev/xive/spapr.c | 2 ++
3 files changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/xive.h b/arch
Hi Javier,
On Wed, Aug 30, 2017 at 9:57 PM, Javier Martinez Canillas
wrote:
>> I think we should talk about the same case: Let me repeat what I did:
>>
>> 1) I added your patch "eeprom: at24: Add OF device ID table"
>> 2) I added an EEPROM node to an I2C
>>
>> + eeprom@50 {
>> +
Some source support MMIO stores on the ESB page to perform EOI. Let's
introduce a specific routine for this case even if this should be the
only use of it.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/sysdev/xive/common.c | 11 ++-
1 file changed, 10 insert
Hello Geert,
On Wed, Aug 30, 2017 at 10:15 PM, Geert Uytterhoeven
wrote:
> Hi Javier,
>
> On Wed, Aug 30, 2017 at 9:57 PM, Javier Martinez Canillas
> wrote:
>>> I think we should talk about the same case: Let me repeat what I did:
>>>
>>> 1) I added your patch "eeprom: at24: Add OF device ID tab
On Wed, 2017-08-30 at 23:17 +1000, Michael Ellerman wrote:
> It's not clear why it makes sense for these to be empty. Either for the
> general idea of the "flush_all_mm()" API, or for your intended use by
> CXL.
Indeed. On hash we don't have a way to flush a PID out of the TLB,
but you can flush t
On Wed, 2017-08-30 at 15:59 +0200, Frederic Barrat wrote:
> > It's not clear why it makes sense for these to be empty. Either for the
> > general idea of the "flush_all_mm()" API, or for your intended use by
> > CXL.
>
> I was not too sure what to do for hash, but the idea is that the new
> flush
Hi Pavel,
[auto build test ERROR on sparc/master]
[also build test ERROR on v4.13-rc7 next-20170829]
[cannot apply to mmotm/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Pavel-Tatashin/
Hi Gregory,
Gregory Fong writes:
> Hi all,
>
> In arch/powerpc/sysdev/mpic.c , it looks like IRQ_TYPE_EDGE_BOTH is
> handled the same way as IRQ_TYPE_EDGE_FALLING:
>
> static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
> {
> /* Now convert sense value */
>
Hi Pavel,
[auto build test ERROR on sparc/master]
[also build test ERROR on v4.13-rc7 next-20170829]
[cannot apply to mmotm/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Pavel-Tatashin/
Hi Arnaldo,
Please pull an update to the JSON files for POWER9 PMU events. This
removes alternate event codes from the JSON files which seem to confuse
perf.
The following changes since commit 1b2f76d77a277bb70d38ad0991ed7f16bbc115a9:
Merge tag 'perf-core-for-mingo-4.14-20170829' of
git://gi
Michael Neuling [mi...@neuling.org] wrote:
> Suka,
>
> Please CC Christophe who as an alternative way of doing this. We ned to get
> agreement across all users of TIDR/AS_notify...
Mikey,
Thanks. There is overlap between the two patches. I will send a patch on
top of Christophe's for the interfa
On Wed, Aug 30, 2017 at 07:45:17PM +1000, Paul Mackerras wrote:
> On Tue, Aug 29, 2017 at 07:18:01PM -0300, Jose Ricardo Ziviani wrote:
> > Hello!
> >
> > This patch implements MMIO emulation for two instructions: lvx and stvx. I
> > started to implement other instructions but I'd like to have th
Tested-by: Michael Neuling
FWIW I've written a test case for alignment faults (which I'll convert to a
selftest and upstream). It tests all load stores supported by POWER9 (results
below).
VSX: 2.06B
Doing lxvd2x: PASSED
Doing lxvw4x: PASSED
Doing lxsdx:PASSED
On Thu, 2017-08-31 at 10:49 +1000, Michael Neuling wrote:
> Tested-by: Michael Neuling
>
> FWIW I've written a test case for alignment faults (which I'll convert to a
> selftest and upstream). It tests all load stores supported by POWER9 (results
> below).
Sorry, this is not quite right. It doe
On 31/08/17 05:02, Bjorn Helgaas wrote:
> On Fri, Aug 11, 2017 at 06:19:33PM +1000, Alexey Kardashevskiy wrote:
>> From: Gavin Shan
>>
>> The PowerNV platform is the only user of pcibios_sriov_disable().
>> The IOV BAR could be shifted by pci_iov_update_resource(). The
>> warning message in the fu
From: Benjamin Herrenschmidt
From: Alexey Kardashevskiy
This updates the comment about creating a hole in /proc/iomem which
should not be normally happening but it does in the powernv platform
due the way MMIO M64 BARs are organised in the IODA2-capable hardware.
Signed-off-by: Alexey Kardashe
On Thu, Jul 13, 2017 at 10:38:29AM +0300, Dan Carpenter wrote:
> There are some error paths in kvmppc_core_vcpu_create_e500() where we
> forget to set the error code. It means that we return ERR_PTR(0) which
> is NULL and it results in a NULL pointer dereference in the caller.
>
> Signed-off-by:
On Sun, Aug 13, 2017 at 11:33:38AM +1000, Nicholas Piggin wrote:
> KVM currently validates the size of the VPA registered by the client
> against sizeof(struct lppaca), however we align (and therefore size)
> that struct to 1kB to avoid crossing a 4kB boundary in the client.
>
> PAPR calls for siz
On Tue, Aug 15, 2017 at 02:37:01PM +1000, Michael Ellerman wrote:
> From: Andreas Schwab
>
> binutils >= 2.26 now warns about misuse of register expressions in
> assembler operands that are actually literals. In this instance r0 is
> being used where a literal 0 should be used.
>
> Signed-off-by
On 08/30/2017 03:02 PM, Laurent Dufour wrote:
> On 30/08/2017 07:58, Peter Zijlstra wrote:
>> On Wed, Aug 30, 2017 at 10:33:50AM +0530, Anshuman Khandual wrote:
>>> diff --git a/mm/filemap.c b/mm/filemap.c
>>> index a497024..08f3042 100644
>>> --- a/mm/filemap.c
>>> +++ b/mm/filemap.c
>>> @@ -1181,
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