Hi Mpe, Thanks for reviewing the patch
Michael Ellerman <m...@ellerman.id.au> writes: >> + ctx->elem->software_state = cpu_to_be32(CXL_PE_SOFTWARE_STATE_V); >> + /* Make sure the changes to the PE are visible to the card */ > > A barrier orders something vs something else. So what's the something > else in this case? Is it the afu_reset() below, what does that actually do? > The issue is with call to afu_enable() after the call to afu_reset that would start the AFU. If this load gets reordered and PSL doesnt see the valid bit set for this structure then it will result in PSL entering a freeze-state. Though on second thoughts afu_enable() is grabbing a spin-lock before doing an mmio to start the AFU that would be forcing a barrier anyways. But since that spans the function boundary hence to be safe have added a write barrier after populating the process element. Lastly function is not performance critical as it will be usually called in the life time of a process only once. So the impact smp_wmb() is having would be minimal. -- Vaibhav Jain <vaib...@linux.vnet.ibm.com> Linux Technology Center, IBM India Pvt. Ltd.
