Balbir Singh writes:
> On Wed, 2017-04-05 at 10:49 +0530, Anshuman Khandual wrote:
>> diff --git a/arch/powerpc/include/uapi/asm/mman.h
>> b/arch/powerpc/include/uapi/asm/mman.h
>> index 03c06ba..3eb788c 100644
>> --- a/arch/powerpc/include/uapi/asm/mman.h
>> +++ b/arch/powerpc/include/uapi/asm/m
Add 32 and 8 bit variants
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/bitops.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/include/asm/bitops.h
b/arch/powerpc/include/asm/bitops.h
index bc5fdfd..33a24fd 100644
--- a/arch/powerpc/include/asm/bi
Some platforms (will) need to perform allocations before bringing
a new CPU online. Doing it from smp_ops->setup_cpu is the wrong
thing to do:
- It has no useful failure path (too late)
- Calling any allocator will enable interrupts prematurely
causing problems with large decrementer among ot
It's only used within the same file it's defined
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/kvm_ppc.h | 4
arch/powerpc/kvm/book3s_xics.c | 2 +-
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/incl
We need to set LPES in order for normal external interrupts (0x500)
to be directed to the guest while running in guest state.
We also need HEIC set to prevent them to be sent to the host while
in host state.
With XIVE the host never gets one of these and wouldn't know how to
handle it. All host e
We traditionally have linux/ before asm/
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/kvm/book3s.c| 8
arch/powerpc/kvm/book3s_hv.c | 18 +-
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3
We have all sort of variants of MMIO accessors for the real mode
instructions. This creates a clean set of accessors based on
Linux normal naming conventions, replacing all occurrences of
the old ones in the tree.
I have purposefully removed the "out/in" variants in favor of
only including __raw v
The function doesn't exist anymore
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/kvm_ppc.h | 4
1 file changed, 4 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index bfef1ae..0c41865 100644
--- a/arch/powerpc/include
Some powerpc platforms use this to move IRQs away from a CPU
being unplugged. This function has several bugs such as not
taking the right locks or failing to NULL check pointers.
There's a new generic function doing exactly the same thing
without all the bugs, so let's use it instead.
Signed-off-
This patch makes KVM capable of using the XIVE interrupt controller
to provide the standard PAPR "XICS" style hypercalls. It is necessary
for proper operations when the host uses XIVE natively.
This has been lightly tested on an actual system, including PCI
pass-through with a TG3 device.
Signed-
The XIVE interrupt controller is the new interrupt controller
found in POWER9. It supports advanced virtualization capabilities
among other things.
Currently we use a set of firmware calls that simulate the old
"XICS" interrupt controller but this is fairly inefficient.
This adds the framework fo
Most distros will want it on by default and I've missed
turning it on during developer testing. Having it on ensures
we are testing our patches with the config enabled.
Signed-off-by: Balbir Singh
---
arch/powerpc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/Kconfig b
Le 03/04/2017 à 14:27, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment. These t
Laurentiu Tudor writes:
> Hi Michael,
>
> Just a couple of basic things to check:
> - was the dtb updated to the newest?
Possibly not, it's an automated build/boot, I'll have to check what it
does with the dtb.
> - is the qman node present? This should be easily visible in
> /proc/device-t
Hi Vaibhav,
I like the simplified version better. However, I think it breaks
cxlflash's recovery. With this patch, we are also unlocking the adapter
later. It doesn't matter when the driver initializes the first time, but
on EEH, we now call the "slot reset" callback of the virtual device
whi
This just adds user space exported ABI definitions for 2MB, 16MB, 1GB,
16GB non default huge page sizes to be used with mmap() system call.
Signed-off-by: Anshuman Khandual
---
These defined values will be used along with MAP_HUGETLB while calling
mmap() system call if the desired HugeTLB page si
During an eeh event when the cxl card is fenced and card sysfs attr
perst_reloads_same_image is set following warning message is seen in the
kernel logs:
[ 60.622727] Adapter context unlocked with 0 active contexts
[ 60.622762] [ cut here ]
[ 60.622771] WARNING: CP
From: Oliver O'Halloran
When the kernel is compiled to use 64bit ABIv2 the _GLOBAL() macro does
not include a global entry point. A function's global entry point is
used when the function is called from a different TOC context and in the
kernel this typically means a call from a module into the v
On 04/05/2017 01:06 PM, Michael Ellerman wrote:
> Laurentiu Tudor writes:
>
>> Hi Michael,
>>
>> Just a couple of basic things to check:
>>- was the dtb updated to the newest?
>
> Possibly not, it's an automated build/boot, I'll have to check what it
> does with the dtb.
>
>>- is the qma
On 04/04/2017 07:34 PM, Aneesh Kumar K.V wrote:
> The right interface to use to set a hugetlb pte entry is set_huge_pte_at. Use
> that instead of set_pte_at.
This is a generic change, should not mm list be added for this patch.
Michael Ellerman writes:
> Oliver O'Halloran writes:
>
>> When the kernel is compiled to use 64bit ABIv2 the _GLOBAL() macro does not
>> include a global entry point. A function's global entry point is used when
>> the
>> function is called from a different TOC context and in the kernel this
>>
On Tuesday 04 April 2017 07:11 AM, Daniel Axtens wrote:
Madhavan Srinivasan writes:
From: Hemant Kumar
Parse device tree to detect IMC units. Traverse through each IMC unit
node to find supported events and corresponding unit/scale files (if any).
Here is the DTS file for reference:
Le 03/04/2017 à 14:39, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL:
- Init implementation for the adapter and the afu.
- Invalidate TLB/SLB.
Hi,
This is the latest cpufeatures series for Linux. It should be
close to merge now I hope, but another round of review would
be good.
If we can merge the first minor patches and get those out of
the way it would be helpful.
Thanks,
Nick
POWER9/ISAv3 has no VRMASD field in LPCR. Don't set reserved bits.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/cpu_setup_power.S | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_
Introduce primitives for FDT parsing. These will be used for powerpc
cpufeatures node scanning, which has quite complex structure but should
be processed early.
Signed-off-by: Nicholas Piggin
---
drivers/of/fdt.c | 39 +++
include/linux/of_fdt.h | 6 +++
The /cpus/features dt binding describes architected CPU features along
with some compatibility, privilege, and enablement properties that allow
flexibility with discovering and enabling capabilities.
Presence of this feature implies a base level of functionality, then
additional feature nodes adve
Andreas Schwab writes:
> On Apr 04 2017, Michael Ellerman wrote:
>
>> Quick quiz, who still has a POWER4?
>
> Does a G5 qualify?
Not really, I have one (actually several) of those :)
And G5/POWER4 are not 100% equivalent as far as the kernel is concerned.
>> And if so are you running mainline
Denis Kirjanov writes:
> On 4/4/17, Michael Ellerman wrote:
>> Hi folks,
>>
>> Quick quiz, who still has a POWER4?
>>
>> And if so are you running mainline on it?
>
> Not the same thing, but I have a box on two 970MP
Yeah not 100% the same. Thanks for testing 970MP.
cheers
According to the PowerISA 2.07, mtspr and mfspr should not always
generate an illegal instruction exception when being used with an
undefined SPR, but rather treat the instruction as a NOP or inject a
privilege exception in some cases, too - depending on the SPR number.
Also turn the printk here in
From: Nicholas Piggin
Date: Tue, 4 Apr 2017 13:02:33 +1000
> On Mon, 3 Apr 2017 17:43:05 -0700
> Linus Torvalds wrote:
>
>> But that depends on architectures having some pattern that we *can*
>> abstract. Would some "begin/in-loop/end" pattern like the above be
>> sufficient?
>
> Yes. begin/in
On Wednesday 05 April 2017 05:21 PM, Anshuman Khandual wrote:
On 04/04/2017 07:34 PM, Aneesh Kumar K.V wrote:
The right interface to use to set a hugetlb pte entry is set_huge_pte_at. Use
that instead of set_pte_at.
This is a generic change, should not mm list be added for this patch.
ye
On Wed, Apr 5, 2017 at 9:32 AM, Nicholas Piggin wrote:
> On Wed, 5 Apr 2017 08:35:06 -0500
> Rob Herring wrote:
>
>> On Wed, Apr 5, 2017 at 7:37 AM, Nicholas Piggin wrote:
>> > Introduce primitives for FDT parsing. These will be used for powerpc
>> > cpufeatures node scanning, which has quite co
From: Aravinda Prasad
This patch introduces a new KVM capability to control
how KVM behaves on machine check exception (MCE).
Without this capability, KVM redirects machine check
exceptions to guest's 0x200 vector, if the address in
error belongs to the guest. With this capability KVM
causes a gu
From: Mahesh Salgaonkar
This patch introduces a mce hook which is invoked at the time of guest
exit to facilitate the host-side handling of machine check exception
before the exception is passed on to the guest. This hook will be invoked
from host virtual mode from KVM (before exiting the guest w
From: Aravinda Prasad
This series of patches add FWNMI support for KVM guests
on POWER.
Memory errors such as bit flips that cannot be corrected
by hardware is passed on to the kernel for handling
by raising machine check exception (an NMI). Upon such
machine check exceptions, if the address in
From: Aravinda Prasad
Enhance KVM to cause a guest exit with KVM_EXIT_NMI
exit reason upon a machine check exception (MCE) in
the guest address space if the KVM_CAP_PPC_FWNMI
capability is enabled (instead of delivering a 0x200
interrupt to guest). This enables QEMU to build error
log and deliver
On Wed, 2017-04-05 at 10:58 -0500, Rob Herring wrote:
> Well, I'd like to avoid expanding usage of flat DT parsing in the
> kernel. But you could just put this function into arch/powerpc and I'd
> never see it, but I like that even less. Mainly, I just wanted to
> raise the point.
>
> Your argumen
Michael, Thanks for the review and comments.
On 04/04/2017 03:55 AM, Michael Ellerman wrote:
> Hi Haren,
>
> A few comments ...
>
> Haren Myneni writes:
>
>> diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
>> index 4e5a470..7315621 100644
>> --- a/arch/powerpc/inc
Hi Benjamin,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.11-rc5 next-20170405]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Benjamin-Herrenschmidt/powerpc-Add-more
On Thu, 2017-04-06 at 06:46 +0800, kbuild test robot wrote:
> Hi Benjamin,
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on v4.11-rc5 next-20170405]
> [if your patch is applied to the wrong git tree, please drop us a
> note to help improve the system]
Oo
Signed-off-by: Benjamin Herrenschmidt
---
That should have been the first patch in the XIVE series...
arch/powerpc/include/asm/opal-api.h| 74 +-
arch/powerpc/include/asm/opal.h| 36 +
arch/powerpc/platforms/powernv/opal-wrappers.S
Hi Benjamin,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.11-rc5 next-20170405]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Benjamin-Herrenschmidt/powerpc-Add-more
On 05/04/17 16:16, Vaibhav Jain wrote:
Fix a boundary condition where in some cases an eeh event that results
in card reset isn't passed on to a driver attached to the virtual PCI
device associated with a slice. This will happen in case when a slice
attached device driver returns a value other th
On Thu, 06 Apr 2017 06:58:01 +1000
Benjamin Herrenschmidt wrote:
> On Wed, 2017-04-05 at 10:58 -0500, Rob Herring wrote:
> > Well, I'd like to avoid expanding usage of flat DT parsing in the
> > kernel. But you could just put this function into arch/powerpc and I'd
> > never see it, but I like th
On Wed, 05 Apr 2017 07:01:57 -0700 (PDT)
David Miller wrote:
> From: Nicholas Piggin
> Date: Tue, 4 Apr 2017 13:02:33 +1000
>
> > On Mon, 3 Apr 2017 17:43:05 -0700
> > Linus Torvalds wrote:
> >
> >> But that depends on architectures having some pattern that we *can*
> >> abstract. Would som
Hi Andrew,
Thanks for reviewing the patch.
Andrew Donnellan writes:
>> Based-on: https://patchwork.ozlabs.org/patch/747102/
>> Fixes: 9e8df8a21963("cxl: EEH support")
>> Signed-off-by: Vaibhav Jain
>
> Reviewed-by: Andrew Donnellan
>
> Should this go to stable?
Yes, Once this patch gets an ac
On Thu, Apr 06, 2017 at 02:17:22AM +0530, Mahesh J Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> This patch introduces a mce hook which is invoked at the time of guest
> exit to facilitate the host-side handling of machine check exception
> before the exception is passed on to the guest. This h
On Wed, 23 Nov 2016 10:40:36 PM Balbir Singh wrote:
>
> > But overall I guess it's OK. We'd want to do a quick benchmark to make
> > sure it's not adding any overhead.
>
> OK.. I'll try and find a benchmark and run it with traces disabled.
For what's it's worth I didn't notice any slow down runnin
Hi Daniel,
Just to respond to your comments,
The inline asm line cannot be formatted over multiple lines due to the
unrolling process, but we can take out the volatile.
The pagefault_disable() also seems to be an old method of disabling
preemption, but no longer actually works to disable preempt
The raid6 Q syndrome check has been optimised using the vpermxor
instruction. This instruction was made available with POWER8, ISA version
2.07. It allows for both vperm and vxor instructions to be done in a single
instruction. This has been tested for correctness on a ppc64le vm with a
basic RAID
Mahesh J Salgaonkar writes:
> From: Mahesh Salgaonkar
>
> This patch introduces a mce hook which is invoked at the time of guest
> exit to facilitate the host-side handling of machine check exception
> before the exception is passed on to the guest. This hook will be invoked
> from host virtual
Alistair Popple writes:
> On Wed, 23 Nov 2016 10:40:36 PM Balbir Singh wrote:
>>
>> > But overall I guess it's OK. We'd want to do a quick benchmark to make
>> > sure it's not adding any overhead.
>>
>> OK.. I'll try and find a benchmark and run it with traces disabled.
>
> For what's it's worth
Hi Matt,
Thanks for answering my questions and doing those fixes.
> Bugs fixed:
> - A small bug in pq.h regarding a missing and mismatched
> ifdef statement
> - Fixed test/Makefile to correctly build test on ppc
>
I think this commit should be labelled:
Fixes: 4f8c55c5ad49 (
On Thu, 2017-04-06 at 16:03 +1000, Michael Ellerman wrote:
> Alistair Popple writes:
>
> > On Wed, 23 Nov 2016 10:40:36 PM Balbir Singh wrote:
> > >
> > > > But overall I guess it's OK. We'd want to do a quick benchmark to make
> > > > sure it's not adding any overhead.
> > >
> > > OK.. I'll tr
On Tuesday 04 April 2017 07:41 AM, Daniel Axtens wrote:
Hi,
Device tree IMC driver code parses the IMC units and their events. It
passes the information to IMC pmu code which is placed in powerpc/perf
as "imc-pmu.c".
This patch creates only event attributes and attribute groups for the
IMC p
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