This file now contain both hash and radix specific code. Rename it to
indicate this better.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/Makefile | 7 +++
arch/powerpc/mm/{mmu_context_hash64.c => mmu_context_book3s64.c} | 0
2 files changed, 3
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 28 ++-
arch/powerpc/include/asm/book3s/64/tlbflush.h | 56 ++
arch/powerpc/include/asm/tlbflush.h| 2 +-
arch/powerpc/mm/tlb_hash64.c |
Core kernel don't track the page size of the va range that we are
invalidating. Hence we end up flushing tlb for the entire mm here.
Later patches will improve this.
We also don't flush page walk cache separetly instead use RIC=2 when
flushing tlb, because we do a mmu gather flush after freeing pa
We are going to add asm changes in the follow up patches. Add the
feature bit now so that we can get it all build. We will enable radix
in the last patch using cpu table.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/mmu.h | 3 ++-
arch/powerpc/include/asm/mmu.h
We also use MMU_FTR_RADIX to branch out from code path specific to
hash.
No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/entry_64.S | 7 +--
arch/powerpc/kernel/exceptions-64s.S | 28 +++-
arch/powerpc/kernel/machine_kexec_
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/lpar.c| 14 +++---
arch/powerpc/platforms/pseries/lparcfg.c | 3 ++-
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/lpar.c
b/arch/powerpc/platforms/pseries/lpar.c
index
Radix don't need slice support. Catch wrong usage of slice feature
with radix enabled
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slice.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index ee21b8699cee..2b27458902
On return from rtas we access the paca variables and we have 64 bit
disabled. This requires us to limit paca in 32 bit range.
Fix this by setting ppc64_rma_size to first_memblock_size/1G range.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-radix.c | 20 +++-
1 file
This is same as the generic code, but then we have to duplicate
because we need to enable enable this along with hash which set
HAVE_ARCH_UNMAPPED_AREA. Hash need special get_unmapped_area handling
because of limitations around base page size. With radix we don't have
such restrictions.
Signed-off
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 8dfc6ae85d4a..be5d123b3f61 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/
This patch start to make a book3s variant for pgalloc headers. We have
multiple book3s specific chanages such as
* 4 level page table
* store physical address in higher level table
* use pte_t * for pgtable_t
Having a book3s 64 specific variant helps to keep code simpler and
remove lots of #ifdef
This moves the nohash variant of pgalloc headers to nohash/ directory
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 6 +++---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 17 ++--
arch/powerpc/include/asm/book3s/pgalloc.h |
This revert pgalloc related changes w.r.t implementing 4 level page
table for 64k linux page size and storing of physical address in
higher level page table since they are only applicable to book3s 64
variant and we now have a separate copy for book3s 64. This helps to
keep these headers simpler
C
Simplify the code by dropping 4 level page table #ifdef. We are always
4 level now
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 57 +---
1 file changed, 18 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/6
Only code cleanup. No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 12 ++--
arch/powerpc/include/asm/nohash/64/pgalloc.h | 12 ++--
arch/powerpc/mm/pgtable_64.c | 21 -
3 files changed
pgtable_page_dtor for nohash is now moved to pte_fragment_free_mm()
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 147 +++
arch/powerpc/include/asm/nohash/64/pgalloc.h | 38 +--
arch/powerpc/include/asm/page.h | 10 +
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 34
arch/powerpc/include/asm/book3s/64/pgtable.h | 10 ++--
arch/powerpc/mm/hash_utils_64.c | 7 ++
arch/powerpc/mm/pgtable-radix.c | 5 +++-
arch/po
In this patch we make the number of pte fragments per level4 page table
page a variable. Radix level 4 table size is 256 bytes and hence we
can have 256 fragments per level4 page. We don't update the fragment
count in this patch. We need to do performance measurements to find the
right value for fr
With radix there is no mmu cache. Hence we don't need to do much
in update_mmu_cache.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/mem.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index f980da6d7569..3164ce720b3e 100644
--- a/arch/p
---
arch/powerpc/mm/pgtable.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 115a0a19d5a2..0a9658fbf8b9 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -82,6 +82,9 @@ static struct page *maybe_pte_to_page
Radix don't use SLICE framework to find page size. Hence use
vma to find the page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugetlbpage.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
inde
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 14 +++---
arch/powerpc/include/asm/book3s/64/pgtable.h | 15 ---
arch/powerpc/include/asm/book3s/64/radix.h | 21 +
arch/powerpc/kernel/pci_64.c | 3 ++-
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hugetlb-radix.h | 14
arch/powerpc/include/asm/hugetlb.h | 14
arch/powerpc/mm/Makefile | 1 +
arch/powerpc/mm/hugetlbpage-radix.c| 87 ++
With 4k page size radix config our level 1 page table size 64K and it
should naturally aligned
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/head_64.S | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/h
We have hugepage at the pmd level with 4K radix config. Hence we don't
need to use hugepd format with radix.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h| 22 +---
arch/powerpc/include/asm/book3s/64/pgtable-4k.h | 46 +
2 fi
THP is only supported by hash64 now and for that we should always
have PTE_ATOMIC_UPDATES always set. Drop the unnecessary #ifdef
in the code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable_64.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/mm
Only code movement in this patch. No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 24 +-
arch/powerpc/mm/pgtable-hash64.c | 363 ++-
arch/powerpc/mm/pgtable_64.c | 360 ---
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h| 23 +++-
arch/powerpc/include/asm/book3s/64/pgtable-64k.h | 42 +--
arch/powerpc/include/asm/book3s/64/pgtable.h | 83 +++---
arch/powerpc/mm/Makefile | 2 +-
arch/p
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 59
arch/powerpc/include/asm/book3s/64/pgtable-64k.h | 25 --
arch/powerpc/include/asm/book3s/64/pgtable.h | 22 +
arch/powerpc/platforms/Kconfig.cputype |
The deposited pgtable_t is a pte fragment hence we cannot use page->lru
for linking then together. We use the first two 64 bits for pte fragment
as list_head type to link all deposited fragments together. On withdraw
we properly zero then out.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/inc
With P9 Radix we need to do
* set UPRT = 1
* set different TLB set count
In this patch we delay the UPRT=1 to early mmu init. This help us to
keep the cpu table setup and restore cpu callback the same across
different MMU model.
This also implies that a cpu_restore cur_cpu_spec callback won't se
We can depend on ibm,pa-features to enable/disable radix. This gives us
a nice way to test p9 hash config, by changing device tree property.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/prom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerp
On Fri, Apr 8, 2016 at 2:13 PM, Rafał Miłecki wrote:
> 1) Use pr_fmt to keep messages consistent
> 2) Don't warn if kzalloc fails as it dumps stack on its own
> 3) Use %pR format for displaying whole resource to avoid:
> warning: format ‘%08llx’ expects type ‘long long unsigned int’, but argument
On Fri, Apr 08, 2016 at 12:27:44AM -0500, Nathan Fontenot wrote:
> On 04/06/2016 04:44 AM, Bharata B Rao wrote:
> > memory_hotplug_max() uses hot_add_drconf_memory_max() to get maxmimum
> > addressable memory by referring to ibm,dyanamic-memory property. There
> > are three problems with the curren
On 2016/04/08 04:57PM, Balbir Singh wrote:
> On Thu, 2016-04-07 at 14:56 +0530, Naveen N. Rao wrote:
> > On 2016/04/07 06:19PM, Balbir Singh wrote:
> > >
> > >
> > > On 06/04/16 22:32, Naveen N. Rao wrote:
> > > >
> > > > This patchset fixes three issues found with perf probe on ppc64le:
> > > >
Hi Michael
The other day, I was curious how the vdso was implemented on ppc, and I
noted that neither ppc32 or ppc64 handle the _COARSE versions of
CLOCK_{REALTIME,MONOTONIC} in the vdso, so they fall back to an actual
syscall. And sure enough, measuring CLOCK_MONOTONIC
vs. CLOCK_MONOTONIC_COARSE
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