On Thu, 2016-02-25 at 10:39 +1100, Balbir Singh wrote:
> On 25/02/16 01:28, Michael Ellerman wrote:
> > is_early_mcount_callsite() needs to detect either the two instruction or
> > the three instruction versions of the _mcount() sequence.
> >
> > But if we're running a kernel with the two instruct
On Thu, 2016-02-25 at 11:28 +1100, Balbir Singh wrote:
> On 25/02/16 01:28, Michael Ellerman wrote:
> > @@ -300,8 +298,34 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned
> > long addr)
> > * The load offset is different depending on the ABI. For simplicity
> > * just mask it out w
On Thu, 2016-02-25 at 11:30 +1100, Balbir Singh wrote:
>
> On 25/02/16 01:28, Michael Ellerman wrote:
> > Signed-off-by: Michael Ellerman
> >
> > diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
> > index 2a7313cfbc7d..9e77a2c8f218 100644
> > --- a/arch/powerpc/kernel
On Thu, 2016-02-25 at 11:08 +1100, Balbir Singh wrote:
>
> On 25/02/16 01:28, Michael Ellerman wrote:
> > In order to support the new -mprofile-kernel ABI, we need to be able to
> > call from the module back to ftrace_caller() (in the kernel) without
> > using the module's r2. That is because the
Signed-off-by: Alessio Igor Bogani
---
arch/powerpc/boot/dts/{ => fsl}/gef_ppc9a.dts| 0
arch/powerpc/boot/dts/{ => fsl}/gef_sbc310.dts | 0
arch/powerpc/boot/dts/{ => fsl}/gef_sbc610.dts | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8641_hpcn.dts | 0
arch/powerpc/boot/dts/{ =>
Signed-off-by: Alessio Igor Bogani
---
arch/powerpc/boot/dts/fsl/gef_ppc9a.dts| 284 +++---
arch/powerpc/boot/dts/fsl/gef_sbc310.dts | 276 +++--
arch/powerpc/boot/dts/fsl/gef_sbc610.dts | 284 +++---
arch/powerpc/boot/dts/fsl/mp
Hi Linus,
Please pull a couple more powerpc fixes for 4.5:
The following changes since commit 6ecad912a0073c768db1491c27ca55ad2d0ee68f:
powerpc/ioda: Set "read" permission when "write" is set (2016-02-17 23:52:17
+1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/
On 02/25/2016 12:35 PM, Shreyas B Prabhu wrote:
>
>
> On 02/25/2016 10:25 AM, Mahesh J Salgaonkar wrote:
>> From: Mahesh Salgaonkar
>>
>> The current implementation of MCE early handling modifies CR0/1 registers
>> without saving its old values. Fix this by moving early check for
>> powersaving
On Thu, Feb 25, 2016 at 01:28:24AM +1100, Michael Ellerman wrote:
> Currently we generate the module stub for ftrace_caller() at the bottom
> of apply_relocate_add(). However apply_relocate_add() is potentially
> called more than once per module, which means we will try to generate
> the ftrace_cal
Le 24/02/2016 21:03, Manoj Kumar a écrit :
From: Christophe Lombard
+#define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3
(dedicated/master/shared) */
Where does this limit of 4 AFUs come from?
Is this related to CXL_MAX_SLICES?
Should this be a computed value, in case the number of AFUs/
On Thu, Feb 25, 2016 at 01:28:25AM +1100, Michael Ellerman wrote:
>
> We can make that process easier by marking the generated stubs with a
> magic value, and then looking for that magic value. Altough this is not
> as rigorous as the current method, I believe it is sufficient in
> practice.
The
Le 24/02/2016 21:15, Manoj Kumar a écrit :
On 2/23/2016 10:21 AM, Frederic Barrat wrote:
+module_init(cxl_base_init);
Is this a remnant from when there were two modules?
Do you really need two module_init() calls (can't one be called from the
other)?
What is the tear-down portion of this (mo
On Thu, Feb 25, 2016 at 11:08:54AM +1100, Balbir Singh wrote:
> How about some comments on r2
> r2 is still pointing to the module's toc, will be saved by ftrace_caller and
> restored by the instruction following bl ftrace_caller (after patching
> _mcount/nop)
To be precise: ftrace_caller needs
On Thu, Feb 25, 2016 at 01:28:27AM +1100, Michael Ellerman wrote:
> @@ -450,17 +448,44 @@ static unsigned long stub_for_addr(const Elf64_Shdr
> *sechdrs,
> return (unsigned long)&stubs[i];
> }
>
> +#ifdef CC_USING_MPROFILE_KERNEL
> +static int is_early_mcount_callsite(u32 *instruction)
>
On Thu, Feb 25, 2016 at 11:30:38AM +1100, Balbir Singh wrote:
> On 25/02/16 01:28, Michael Ellerman wrote:
> > Signed-off-by: Michael Ellerman
> > ---
> > arch/powerpc/kernel/entry_64.S | 8
> > 1 file changed, 8 insertions(+)
> >
Ah, -mprofile-kernel, DYNAMIC_FTRACE but without REGS.
H
On Thu, Feb 25, 2016 at 09:28:32PM +1100, Michael Ellerman wrote:
> On Thu, 2016-02-25 at 10:39 +1100, Balbir Singh wrote:
> > On 25/02/16 01:28, Michael Ellerman wrote:
> > > is_early_mcount_callsite() needs to detect either the two instruction or
> > > the three instruction versions of the _mcoun
On Thu, Feb 25, 2016 at 01:28:31AM +1100, Michael Ellerman wrote:
> The main change is to just use paca->kernel_toc, rather than a branch to
> +4 and mflr etc. That makes the code simpler and should also perform
> better.
Indeed.
> There was also a sequence after ftrace_call() where we load from
On Thu, Feb 25, 2016 at 12:11:33PM +1100, Balbir Singh wrote:
> On 25/02/16 01:28, Michael Ellerman wrote:
> >
> > diff --git a/arch/powerpc/gcc-mprofile-kernel-notrace.sh
> > b/arch/powerpc/gcc-mprofile-kernel-notrace.sh
> > new file mode 100755
> > index ..68d6482d56ab
> > --- /dev/n
* Michael Ellerman [2016-02-25 01:28:24]:
> Currently we generate the module stub for ftrace_caller() at the bottom
> of apply_relocate_add(). However apply_relocate_add() is potentially
> called more than once per module, which means we will try to generate
> the ftrace_caller() stub multiple ti
On Thu, Feb 25, 2016 at 11:48:59AM +1100, Balbir Singh wrote:
> > @@ -608,6 +621,9 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
> > return -ENOENT;
> > if (!restore_r2((u32 *)location + 1, me))
> >
On 23 February 2016 at 18:47, Will Deacon wrote:
> [adding Steve, since he worked on THP for 32-bit ARM]
Apologies for my late reply...
>
> On Tue, Feb 23, 2016 at 07:19:07PM +0100, Gerald Schaefer wrote:
>> On Tue, 23 Feb 2016 13:32:21 +0300
>> "Kirill A. Shutemov" wrote:
>> > The theory is th
On Thu, Feb 25, 2016 at 03:49:33PM +, Steve Capper wrote:
> On 23 February 2016 at 18:47, Will Deacon wrote:
> > [adding Steve, since he worked on THP for 32-bit ARM]
>
> Apologies for my late reply...
>
> >
> > On Tue, Feb 23, 2016 at 07:19:07PM +0100, Gerald Schaefer wrote:
> >> On Tue, 23
On 25 February 2016 at 16:01, Kirill A. Shutemov wrote:
> On Thu, Feb 25, 2016 at 03:49:33PM +, Steve Capper wrote:
>> On 23 February 2016 at 18:47, Will Deacon wrote:
>> > [adding Steve, since he worked on THP for 32-bit ARM]
>>
>> Apologies for my late reply...
>>
>> >
>> > On Tue, Feb 23,
Fred: Thanks for the clarification.
Reviewed-by: Manoj Kumar
---
Manoj Kumar
On 2/25/2016 7:19 AM, Frederic Barrat wrote:
Le 24/02/2016 21:15, Manoj Kumar a écrit :
On 2/23/2016 10:21 AM, Frederic Barrat wrote:
+module_init(cxl_base_init);
Is this a remnant from when there were two mod
Fred: Comments below.
On 2/25/2016 7:11 AM, Frederic Barrat wrote:
Le 24/02/2016 21:03, Manoj Kumar a écrit :
From: Christophe Lombard
+#define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3
(dedicated/master/shared) */
Where does this limit of 4 AFUs come from?
Is this related to CXL_MAX
On Wed, 24 Feb 2016, Hugh Dickins wrote:
> On Thu, 25 Feb 2016, Aneesh Kumar K.V wrote:
> >
> > Can you test the impact of the merge listed below ?(ie, revert the merge
> > and see if
> > we can reproduce and also verify with merge applied). This will give us a
> > set of commits to look closer.
On Thu, 25 Feb 2016 11:52:05 +0530
"Naveen N. Rao" wrote:
> On 2016/02/25 10:44AM, Cyril Bur wrote:
> > On Wed, 24 Feb 2016 19:57:38 +0530
> > "Naveen N. Rao" wrote:
> >
> > > On 2016/02/23 02:38PM, Cyril Bur wrote:
> > > > Test that the non volatile floating point and Altivec registers get
This applies on top of the patches posted by Michael today
Enable livepatching. This takes patch 6/8 and 7/8 of v8 as the base.
Removes the extra strict check in gcc-profile-kernel-notrace.sh
and adds logic for checking offsets in livepatch. The patch
for HAVE_C_RECORDMCOUNT is not required and not
* Balbir Singh [2016-02-25 23:11:45]:
> This applies on top of the patches posted by Michael today
> Enable livepatching. This takes patch 6/8 and 7/8 of v8 as the base.
> Removes the extra strict check in gcc-profile-kernel-notrace.sh
> and adds logic for checking offsets in livepatch. The patch
On 01/12, Lothar Waßmann wrote:
> This patchset adds the clock which is necessary to operate the KPP
> unit on i.MX6UL.
> The first patch removes bogus whitespace before TABs in indentation.
> The second patch adds the clock definition.
>
Both look fine. Shawn?
--
Qualcomm Innovation Center, In
When we have partial hotplug as part of the error recovery on PF,
the VFs that are bound with vfio-pci driver will experience hotplug.
That's not allowed.
This checks if the VF PE is passed or not. If it does, we leave
the VF without removing it.
Signed-off-by: Gavin Shan
---
arch/powerpc/kerne
Those patches are based on the series of patches supporting EEH for VF,
which is pending for merging: https://patchwork.ozlabs.org/patch/581315/
This series of patches fixes couple of issue that resides in previous
patchset:
* The error handlers provided by vfio-pci driver shouldn't be called.
When EEH error happened to the parent PE of those PEs that have
been passed through to guest, the error is propagated to guest
domain and the VFIO driver's error handlers are called. It's not
correct as the error in the host domain shouldn't be propagated
to guests and affect them.
This adds one m
When passing through SRIOV VFs to guest, we possibly encounter EEH
error on PF. In this case, the VF PEs are put into frozen state.
The error could be reported to guest before it's captured by the
host. That means the guest could attempt to recover errors on VFs
before host gets chance to recover e
When eeh_dump_pe_log() is only called by eeh_slot_error_detail(),
we already have the check that the PE isn't in PCI config blocked
state in eeh_slot_error_detail(). So we needn't the duplicated
check in eeh_dump_pe_log().
This removes the duplicated check in eeh_dump_pe_log(). No logical
changes
On Tue, Feb 16, 2016 at 10:58:20AM +1100, Andrew Donnellan wrote:
>On 16/02/16 10:30, Gavin Shan wrote:
>>Thanks for review. Do you want to see revised patch to include your
>>comments?
>
>Not particularly - the comments were just detailing what I went through as I
>reviewed it. Feel free to includ
The function is used to update the MMU with software PTE. It can
be called by data access exception handler (0x300) or instruction
access exception handler (0x400). If the function is called by
0x400 handler , the local variable @access is set to _PAGE_EXEC
to indicate the software PTE should have
When the page fault happened in user space, we need check it's
caused by stack frame pointer update instruction and update
local variable @flag with FAULT_FLAG_USER. Currently, the code
has two separate check for the same condition. That's unnecessary.
This removes one of the duplicated check. No
Paul Mackerras writes:
> On Tue, Feb 23, 2016 at 10:18:08AM +0530, Aneesh Kumar K.V wrote:
>> This is needed so that we can support both hash and radix page table
>> using single kernel. Radix kernel uses a 4 level table.
>>
>> Signed-off-by: Aneesh Kumar K.V
>> ---
>> arch/powerpc/Kconfig
Paul Mackerras writes:
> On Tue, Feb 23, 2016 at 10:18:09AM +0530, Aneesh Kumar K.V wrote:
>> We now use physical address in upper page table tree levels. Even though
>> they are aligned to their size, for the masked bits we use the
>> overloaded bit positions as per PowerISA 3.0. We keep the bad
Paul Mackerras writes:
> On Tue, Feb 23, 2016 at 10:18:10AM +0530, Aneesh Kumar K.V wrote:
>> This patch make a copy of pgalloc routines for book3s. The idea is to
>> enable a hash64 copy of these pgalloc routines which can be later
>> updated to have a radix conditional. Radix introduce a new pa
Now that we have _PAGE_READ use that to implement prot none. With this
prot_none is _PAGE_PRESENT with none of the access bits set. While
hashing we map that to PP bit 00.
With this implementation, we will now take a prot fault for prot none
ptes, whereas before, we never inserted such a pte to ha
_PAGE_PRIV means the page can be accessed only by kernel. This is done
to keep pte bits similar to PowerISA 3.0 radix PTE format. User
pages are now makred by clearing _PAGE_PRIV bit.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 23 ++-
arch
This enables us to share the same page table code for
both radix and hash. Radix use a hardware defined big endian
page table
Asm -> C conversion makes it simpler to build code for both little
and big endian page table.
Signed-off-by: Aneesh Kumar K.V
---
Note:
Any suggestion on how we can do th
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