This patch enables SW based post processing of BHRB captured branches
to be able to meet more user defined branch filtration criteria in perf
branch stack sampling framework. These changes increase the number of
branch filters and their valid combinations on any powerpc64 server
platform with BHRB
This patch cleans up some existing indentation problem in code and
re organizes the BHRB processing code with an helper function named
'update_branch_entry' making it more readable. This patch does not
change any functionality.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-book3s.c
This patch simply changes the name of the variable from 'bhrb_filter' to
'bhrb_hw_filter' in order to add one more variable which will track SW
filters in generic powerpc book3s code which will be implemented in the
subsequent patch. This patch does not change any functionality.
Signed-off-by: Ans
The kernel now supports SW based branch filters for book3s systems with
some specific requirements while dealing with HW supported branch filters
in order to achieve overall OR semantics prevailing in perf branch stack
sampling framework. This patch adapts the BHRB branch filter configuration
to me
Generic powerpc branch analysis support added in the code patching
library which will help the subsequent patch on SW based filtering
of branch records in perf.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/code-patching.h | 15
arch/powerpc/lib/code-patching.c |
The new IFC controller version 2.0 has a different memory map page.
Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0 PAGE size is 64KB.
This patch segregates the IFC global and runtime registers to appropriate
PAGE sizes.
Signed-off-by: Jaiprakash Singh
Signed-off-by: Raghav Dogra
Acked-by: Li Yan
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Tuesday, February 16, 2016 6:12 AM
> To: Raghav Dogra ; Brian Norris
> ; Li Yang
> Cc: Raghav Dogra ; linux-...@lists.infradead.org;
> linuxppc-dev ; Prabhakar Kushwaha
> ; Jaiprakash Singh
>
> Subject: Re: [PATC
Le 14/02/2016 21:40, Denis Kirjanov a écrit :
On 2/11/16, Christophe Leroy wrote:
This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
PPC32 doesn't have the PACA structure, so we use the task_info
structure to store the accounting data.
In order to reuse on PPC32 the PPC64 functions,
This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
PPC32 doesn't have the PACA structure, so we use the task_info
structure to store the accounting data.
In order to reuse on PPC32 the PPC64 functions, all u64 data has
been replaced by 'unsigned long' so that it is u32 on PPC32 and
u64
Hi guys,
Sorry I haven't been keeping up to date with this thread I've been away.
On Thu, 2016-02-11 at 09:42 +0100, Torsten Duwe wrote:
> On Thu, Feb 11, 2016 at 06:48:17PM +1100, Balbir Singh wrote:
> > On Wed, 2016-02-10 at 17:25 +0100, Torsten Duwe wrote:
> > > +
> > > +echo "int func() { ret
Hi folks,
FYI I've rebased my fixes branch.
Unfortunately we had a couple of fixes in fixes that needed fixes in order to
be actual fixes.
So if you're basing some work on it you'll have to fetch and rebase.
The old head commit was: 0fe53e8d335bfc02f81300b70211e61fb931a725
and now it
On Fri, 2016-02-12 at 17:09 +1100, Gavin Shan wrote:
> On Fri, Feb 12, 2016 at 05:02:46PM +1100, Andrew Donnellan wrote:
> > On 09/02/16 15:50, Gavin Shan wrote:
> > > When PCI bus is unplugged during full hotplug for EEH recovery,
> > > the platform PE instance (struct pnv_ioda_pe) isn't releas
Balbir Singh writes:
>> Now we can't depend for mm_cpumask, a parallel find_linux_pte_hugepte
>> can happen outside that. Now i had a variant for kick_all_cpus_sync that
>> ignored idle cpus. But then that needs more verification.
>>
>> http://article.gmane.org/gmane.linux.ports.ppc.embedded/811
Michael Ellerman writes:
> Hi folks,
>
> FYI I've rebased my fixes branch.
>
> Unfortunately we had a couple of fixes in fixes that needed fixes in order to
> be actual fixes.
>
> So if you're basing some work on it you'll have to fetch and rebase.
>
> The old head commit was: 0fe53e8d335bfc02f81
On Sat, Feb 13, 2016 at 12:58:31PM +0100, Sebastian Ott wrote:
>
> On Sat, 13 Feb 2016, Kirill A. Shutemov wrote:
> > Could you check if revert of fecffad25458 helps?
>
> I reverted fecffad25458 on top of 721675fcf277cf - it oopsed with:
>
> ¢ 1851.721062! Unable to handle kernel pointer derefer
On Mon, 15 Feb 2016, Michael Ellerman wrote:
> > > > +echo "int func() { return 0; }" | \
> > > > +$* -S -x c -O2 -p -mprofile-kernel - -o - 2> /dev/null | \
> > > > +sed -n -e '/func:/,/bl _mcount/p' | grep -q TOC
> > > > +
> > > > +leaf_toc_result=$?
> > >
> > > leaf_toc_result failed f
On Mon, Feb 15, 2016 at 09:27:15PM +1100, Michael Ellerman wrote:
>
> There is explicit code in gcc to check whether the TOC setup is needed and
> only
That's undestood. The claim here is: that check is incomplete, at least.
> emit it when it's required. One case where it's *not* required is wh
Hi,
This small set of independent patches tries to fix incorrect
IS_ERR_VALUE macro usage. It fixes most usages leading to errors
as described in [1]. It also follows conclusion from the discussion
[1][2] - IS_ERR_VALUE should be used only with unsigned long type,
signed types should use compariso
IS_ERR_VALUE macro should be used only with unsigned long type.
Otherwise it can work incorrectly.
The patch follows conclusion from discussion on LKML [1][2].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2120927
[2]: http://permalink.gmane.org/gmane.linux.kernel/2150581
Signed-off-by: And
On Mon, 15 Feb 2016, Kirill A. Shutemov wrote:
> > [ 59.851421] list_del corruption. next->prev should be 6e1eb000,
> > but was 0400
>
> This kinda interesting: 0x400 is TAIL_MAPPING.. Hm..
>
> Could you check if you see the problem on commit 1c290f642101 and its
> immediat
On Sat, 13 Feb 2016 01:15:10 +0200
"Kirill A. Shutemov" wrote:
>
> I'm trying to wrap my head around the issue and I don't think missing
> serialization with gup_fast is the cause -- we just don't need it
> anymore.
>
> Previously, __split_huge_page_splitting() required serialization against
>
On 2016/02/15 04:07PM, Cyril Bur wrote:
> Test that the non volatile floating point and Altivec registers get
> correctly preserved across the fork() syscall.
>
> fork() works nicely for this purpose, the registers should be the same for
> both parent and child
>
> Signed-off-by: Cyril Bur
> ---
Hello!
Some architectures provide local transitivity for a chain of threads doing
writes separated by smp_wmb(), as exemplified by the litmus tests below.
The pattern is that each thread writes to a its own variable, does an
smp_wmb(), then writes a different value to the next thread's variable.
On Mon, 15 Feb 2016 13:31:59 +0200
"Kirill A. Shutemov" wrote:
> On Sat, Feb 13, 2016 at 12:58:31PM +0100, Sebastian Ott wrote:
> >
> > On Sat, 13 Feb 2016, Kirill A. Shutemov wrote:
> > > Could you check if revert of fecffad25458 helps?
> >
> > I reverted fecffad25458 on top of 721675fcf277cf
On Mon, Feb 15, 2016 at 09:58:25AM -0800, Paul E. McKenney wrote:
> Hello!
Hi Paul,
> Some architectures provide local transitivity for a chain of threads doing
> writes separated by smp_wmb(), as exemplified by the litmus tests below.
> The pattern is that each thread writes to a its own variabl
On Mon, Feb 15, 2016 at 06:58:32PM +, Will Deacon wrote:
> On Mon, Feb 15, 2016 at 09:58:25AM -0800, Paul E. McKenney wrote:
> > Hello!
>
> Hi Paul,
>
> > Some architectures provide local transitivity for a chain of threads doing
> > writes separated by smp_wmb(), as exemplified by the litmus
@mpe since this patch introduces a new user API I'd appreciate it if you
could give this a bit extra scrutiny.
Excerpts from Frederic Barrat's message of 2016-02-07 00:29:01 +1100:
+Starts and controls flashing a new FPGA image. Partial
+reconfiguration is not supported (yet), so the ima
On Mon, Feb 15, 2016 at 07:37:02PM +0100, Gerald Schaefer wrote:
> On Mon, 15 Feb 2016 13:31:59 +0200
> "Kirill A. Shutemov" wrote:
>
> > On Sat, Feb 13, 2016 at 12:58:31PM +0100, Sebastian Ott wrote:
> > >
> > > On Sat, 13 Feb 2016, Kirill A. Shutemov wrote:
> > > > Could you check if revert of
On Mon, Feb 15, 2016 at 03:04:08PM +0100, Torsten Duwe wrote:
> If you use "-pg -mprofile-kernel", gcc seems to forget that, and omits the TOC
> load, for a similar assembler calling sequence.
>
> Looking at the code I can _understand_ why this is so, but my GCC knowledge
> is not that deep that I
On Mon, Feb 15, 2016 at 09:38:35PM +1100, Michael Ellerman wrote:
>On Fri, 2016-02-12 at 17:09 +1100, Gavin Shan wrote:
>
>> On Fri, Feb 12, 2016 at 05:02:46PM +1100, Andrew Donnellan wrote:
>
>> > On 09/02/16 15:50, Gavin Shan wrote:
>
>> > > When PCI bus is unplugged during full hotplug for EEH r
Excerpts from christophe lombard's message of 2016-02-16 07:53:54 +1100:
> >> +void cxl_guest_reload_module(struct cxl *adapter)
> >> +{
> >> +struct platform_device *pdev;
> >> +int afu;
> >> +
> >> +for (afu = 0; afu < adapter->slices; afu++)
> >> +cxl_guest_remove_afu(adapter
There is a switch fallthough in instr_analyze() which can cause
an invalid instruction to be emulated as a different, valid,
instruction. The rld* (opcode 30) case extracts a sub-opcode from
bits 3:1 of the instruction word. However, the only valid values
of this field a 001 and 000. These cases ar
On Mon, Feb 15, 2016 at 02:25:53PM +1100, Andrew Donnellan wrote:
>On 15/02/16 10:52, Gavin Shan wrote:
>>When eeh_dump_pe_log() is called in eeh_slot_error_detail(), we
>>already have the check that the PE isn't in PCI config blocked
>>state. So we needn't the duplicated check in eeh_dump_pe_log()
On Mon, Feb 15, 2016 at 12:55:08PM +1100, Alexey Kardashevskiy wrote:
> Upcoming multi-tce support (H_PUT_TCE_INDIRECT/H_STUFF_TCE hypercalls)
> will validate TCE (not to have unexpected bits) and IO address
> (to be within the DMA window boundaries).
>
> This introduces helpers to validate TCE an
On 16/02/16 10:30, Gavin Shan wrote:
Thanks for review. Do you want to see revised patch to include your
comments?
Not particularly - the comments were just detailing what I went through
as I reviewed it. Feel free to include it if you feel it makes the
description clearer, but I don't really
On Mon, 15 Feb 2016 22:29:17 +0530
"Naveen N. Rao" wrote:
> On 2016/02/15 04:07PM, Cyril Bur wrote:
> > Test that the non volatile floating point and Altivec registers get
> > correctly preserved across the fork() syscall.
> >
> > fork() works nicely for this purpose, the registers should be the
On Mon, Feb 15, 2016 at 12:55:09PM +1100, Alexey Kardashevskiy wrote:
> This adds real and virtual mode handlers for the H_PUT_TCE_INDIRECT and
> H_STUFF_TCE hypercalls for user space emulated devices such as IBMVIO
> devices or emulated PCI. These calls allow adding multiple entries
> (up to 512)
On Mon, 2016-02-15 at 06:18 +, Raghav Dogra wrote:
>
> > -Original Message-
> > From: Brian Norris [mailto:computersforpe...@gmail.com]
> > Sent: Saturday, February 13, 2016 1:14 AM
> > To: Li Yang
> > Cc: Raghav Dogra ; linux-...@lists.infradead.org;
> > linuxppc-dev ; o...@buserror.
On 16/02/16 10:28, Oliver O'Halloran wrote:
There is a switch fallthough in instr_analyze() which can cause
an invalid instruction to be emulated as a different, valid,
instruction. The rld* (opcode 30) case extracts a sub-opcode from
bits 3:1 of the instruction word. However, the only valid valu
On Tue, Feb 16, 2016 at 11:40:58AM +1100, David Gibson wrote:
> On Mon, Feb 15, 2016 at 12:55:09PM +1100, Alexey Kardashevskiy wrote:
> > This adds real and virtual mode handlers for the H_PUT_TCE_INDIRECT and
> > H_STUFF_TCE hypercalls for user space emulated devices such as IBMVIO
> > devices or
On Tue, Feb 16, 2016 at 12:05:56PM +1100, Paul Mackerras wrote:
> On Tue, Feb 16, 2016 at 11:40:58AM +1100, David Gibson wrote:
> > On Mon, Feb 15, 2016 at 12:55:09PM +1100, Alexey Kardashevskiy wrote:
> > > This adds real and virtual mode handlers for the H_PUT_TCE_INDIRECT and
> > > H_STUFF_TCE h
On Mon, 2016-02-15 at 16:46 +0530, Aneesh Kumar K.V wrote:
> Michael Ellerman writes:
>
> > Hi folks,
> >
> > FYI I've rebased my fixes branch.
> >
> > Unfortunately we had a couple of fixes in fixes that needed fixes in order
> > to
> > be actual fixes.
> >
> > So if you're basing some work on i
On Tue, 2016-12-01 at 04:40:20 UTC, Alexey Kardashevskiy wrote:
> Quite often drivers set only "write" permission assuming that this
> includes "read" permission as well and this works on plenty platforms.
> However IODA2 is strict about this and produces an EEH when "read"
> permission is not and
On Mon, 2016-02-15 at 23:21 +0100, Torsten Duwe wrote:
> On Mon, Feb 15, 2016 at 03:04:08PM +0100, Torsten Duwe wrote:
> > If you use "-pg -mprofile-kernel", gcc seems to forget that, and omits the
> > TOC
> > load, for a similar assembler calling sequence.
> >
> > Looking at the code I can _unde
On 2016/02/16 11:06AM, Cyril Bur wrote:
> On Mon, 15 Feb 2016 22:29:17 +0530
> "Naveen N. Rao" wrote:
>
> > On 2016/02/15 04:07PM, Cyril Bur wrote:
> > > Test that the non volatile floating point and Altivec registers get
> > > correctly preserved across the fork() syscall.
> > >
> > > fork() wo
On Mon, 2016-02-15 at 16:31 +0530, Aneesh Kumar K.V wrote:
> Balbir Singh writes:
>
> > > Now we can't depend for mm_cpumask, a parallel find_linux_pte_hugepte
> > > can happen outside that. Now i had a variant for kick_all_cpus_sync that
> > > ignored idle cpus. But then that needs more verifica
On Tue, 2016-02-16 at 11:06 +1100, Cyril Bur wrote:
> On Mon, 15 Feb 2016 22:29:17 +0530
> "Naveen N. Rao" wrote:
>
> > On 2016/02/15 04:07PM, Cyril Bur wrote:
> > > Test that the non volatile floating point and Altivec registers get
> > > correctly preserved across the fork() syscall.
> > >
> >
* Petr Mladek [2016-02-12 17:45:17]:
[...]
> I guess that you used a broken gcc and cheated the check
> to pass the compilation. Did you, please?
>
> The test used to detect the offset is using a minimalistic
> function is is afftected by the gcc bug.
>
> The patch below might be used to cheat
There is a switch fallthough in instr_analyze() which can cause
an invalid instruction to be emulated as a different, valid,
instruction. The rld* (opcode 30) case extracts a sub-opcode from
bits 3:1 of the instruction word. However, the only valid values
of this field a 001 and 000. These cases ar
Branch record attributes 'mispred' and 'predicted' are single bit
fields as defined in the perf ABI. Hence the data type of the field
'pred' used during BHRB processing should be changed from integer
to bool. This patch also changes the name of the variable from 'pred'
to 'mispred' making the logic
'commit 9de5cb0f6df8 ("powerpc/perf: Add per-event excludes on Power8")'
broke the PMU based BHRB privilege level filter. BHRB depends on the
same MMCR0 bits for privilege level filter which was used to freeze all
the PMCs as a group. Once we moved to individual event based privilege
filters throug
This patch does some code re-arrangements to make it clear that kernel
ignores any separate privilege level branch filter request and does not
support any combinations of HW PMU branch filters.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 22 +++---
1 fil
This is the continuation (rebased and reworked) of the series
posted at https://lkml.org/lkml/2014/5/5/153 (which is V6). I remember
to have incremented the version count for the re-send of the first four
patches of the series to Peter Z for generic review which got pulled in
last year. The
This patch enables privilege mode SW branch filters. Also modifies
POWER8 PMU branch filter configuration so that the privilege mode
branch filter implemented as part of base PMU event configuration
is reflected in bhrb filter mask. As a result, the SW will skip and
not try to process the privilege
This patch adds a test for verifying that all the branch stack
sampling filters supported on powerpc work correctly. It also
adds some assembly helper functions in this regard. This patch
extends the generic event description to handle kernel mapped
ring buffers.
Signed-off-by: Anshuman Khandual
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