On Mon, Feb 08, 2016 at 10:49:28AM -0500, Steven Rostedt wrote:
> On Mon, 8 Feb 2016 16:23:06 +0100
> Petr Mladek wrote:
>
> > >From 2b0fcb678d7720d03f9c9f233b61ed9ed4d420b3 Mon Sep 17 00:00:00 2001
> > From: Petr Mladek
> > Date: Mon, 8 Feb 2016 16:03:03 +0100
> > Subject: [PATCH] ftrace: All
On Fri, 2016-02-05 at 09:36 -0500, Steven Rostedt wrote:
> On Fri, 5 Feb 2016 14:20:17 +0300
> Denis Kirjanov wrote:
> > > > > Signed-off-by: Denis Kirjanov
> > >
> > > Hi Steven,
> > >
> > > please apply with Michael's acked-by tag.
> >
> > ping
>
> Actually, can you take this through the ppc tr
On Tue, 2016-02-09 at 00:38 -0500, David Long wrote:
> From: "David A. Long"
>
> Move duplicate and functionally equivalent code for accessing registers
> and stack (CONFIG_HAVE_REGS_AND_STACK_ACCESS_API) from arch subdirs into
> common kernel files.
>
> I'm sending this out again (with updated d
On Tue, 2016-09-02 at 03:08:30 UTC, Sukadev Bhattiprolu wrote:
> >From 31edd352fb7c2a72913f1977fa1bf168109089ad Mon Sep 17 00:00:00 2001
> From: Sukadev Bhattiprolu
> Date: Tue, 9 Feb 2016 02:47:45 -0500
> Subject: [PATCH] powerpc/perf/hv-gpci: Increase request buffer size
>
> The GPCI hcall allo
* Michael Ellerman wrote:
> On Tue, 2016-02-09 at 00:38 -0500, David Long wrote:
>
> > From: "David A. Long"
> >
> > Move duplicate and functionally equivalent code for accessing registers
> > and stack (CONFIG_HAVE_REGS_AND_STACK_ACCESS_API) from arch subdirs into
> > common kernel files.
> >
On Mon, 2016-01-02 at 06:03:25 UTC, Balbir Singh wrote:
> From: Balbir Singh
>
> I spent some time trying to use kgdb and debugged my inability to
> resume from kgdb_handle_breakpoint(). NIP is not incremented
> and that leads to a loop in the debugger.
>
> I've tested this lightly on a virtual in
On Tue, 2016-02-09 at 16:29 +1100, Andrew Donnellan wrote:
> On 08/02/16 22:31, Michael Ellerman wrote:
> > Pulling the memcons out of the bin_attr here is not all that nice. This
> > routine
> > should really stand on its own without reference to the bin_attr. In theory
> > I
> > might want to d
The main purpose of this patchset is to dramatically reduce the time
spent in DTLB miss handler. This is achieved by:
1/ Mapping RAM with 8M pages
2/ Mapping IMMR with a fixed 512K page
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we ge
We are spending between 40 and 160 cycles with a mean of 65 cycles in
the DTLB handling routine (measured with mftbl) so make it more
simple althought it adds one instruction.
With this modification, we get three registers available at all time,
which will help with following patch.
Signed-off-by:
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTL
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documenta
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19 --
The fixmap related functions try to map kernel pages that are
already mapped through Large TLBs. pte_offset_kernel() has to
return NULL for LTLBs, otherwise the caller will try to access
level 2 table which doesn't exist
Signed-off-by: Christophe Leroy
---
v3: new
v4: no change
v5: no change
v6:
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, and are never defined at the same time.
So rename them x_block_mapped() and define them in the relevant
places
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Functions are mutually exclusive so renamed iaw Scott co
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xf000 : fixmap
* 0xfde0..0xfe00 : consistent mem
* 0xfddf6000..0xfde0 : early ioremap
* 0xc900..0xfddf6000
Once the linear memory space has been mapped with 8Mb pages, as
seen in the related commit, we get 11 millions DTLB missed during
the reference 600s period. 77% of the misses are on user addresses
and 23% are on kernel addresses (1 fourth for linear address space
and 3 fourth for virtual address sp
IMMR is now mapped by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/Kconfig
On recent kernels, with some debug options like for instance
CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough
the kernel code fits in the first 8M.
Today, it is necessary to activate CONFIG_PIN_TLB to get more than 8M
at startup, allthough pinning TLB is not necessary for that.
This
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/mm/init_
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy
---
v2: no change
v3: fix comment as well
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/nohash/32/pgtable.h | 2 +-
arch/powerpc/mm/mmu_decl.h |
Add missing SPRN defines into reg_8xx.h
Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in
reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h
to have it self sufficient, as includers of reg_8xx.h don't all
include asm/page.h
Signed-off-by: Christophe Leroy
---
v2:
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/he
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no chan
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff --
flush/clean/invalidate _dcache_range() functions are all very
similar and are quite short. They are mainly used in __dma_sync()
perf_event locate them in the top 3 consumming functions during
heavy ethernet activity
They are good candidate for inlining, as __dma_sync() does
almost nothing but call
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no ch
clear_pages() is never used expect by clear_page, and PPC32 is the
only architecture (still) having this function. Neither PPC64 nor
any other architecture has it.
This patch removes clear_pages() and moves clear_page() function
inline (same as PPC64) as it only is a few isns
Signed-off-by: Chris
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 i
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2 inse
Remove one instruction in mulhdu
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/kernel/misc_32.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/p
On Mon, 2015-23-11 at 15:01:15 UTC, Douglas Miller wrote:
> Add 'P' command with optional task_struct address to dump all/one task's
> information: task pointer, kernel stack pointer, PID, PPID, state
> (interpreted), CPU where (last) running, and command.
>
> Introduce XMON_PROTECT macro to stand
Modify platform driver suspend/resume to syscore
suspend/resume. This is because p1022ds needs to use
localbus when entering the PCIE resume.
Signed-off-by: Raghav Dogra
---
Changes for v3: rebased to linux.git main branch
arch/powerpc/sysdev/Makefile | 2 +-
arch/powerpc/sysdev/fsl_lbc.c | 4
> On 9 Feb 2016 03:27, "Mike" wrote:
> Ok, so its quirks to be added then? Something not implemented in KMS
> that was in UMS?
> Reports are that the same issue exsist on PPC Amiga Ones with a VIA
> chipset, and the Pegasos 2 with the Artica s chipset, i posted a
> mail from detailiing that.
Just
On Mon, 2015-14-12 at 20:18:06 UTC, Denis Kirjanov wrote:
> ./drmgr -c cpu -a -r gives the following warning:
>
> ...
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/168a20bb35122539682671d15c
cheers
___
Linuxppc-dev mailing list
Li
On Tue, 2016-09-02 at 01:20:31 UTC, "Aneesh Kumar K.V" wrote:
> With ppc64 we use the deposited pgtable_t to store the hash pte slot
> information. We should not withdraw the deposited pgtable_t without
> marking the pmd none. This ensure that low level hash fault handling
> will skip this huge pte
On Fri, 2016-05-02 at 18:50:03 UTC, Andreas Schwab wrote:
> Since binutils 2.26 BFD is doing suffix merging on STRTAB sections. But
> dedotify modifies the symbol names in place, which can also modify
> unrelated symbols with a name that matches a suffix of a dotted name. To
> remove the leading
Hi Scott,
I missed adding you on CC:, Can you take a look at this and make sure we
are not breaking anything on freescale.
"Aneesh Kumar K.V" writes:
> Hello,
>
> This is a large series, mostly consisting of code movement. No new features
> are done in this series. The changes are done to acc
Mike and Gerhard, dont think the situation of the pcie powerpc is bettrer.but
compared with last years with the new kernels and last xorg on a radeonhd 4650
i have an increase of performance about 250x ... example QuakeSpasm was gaving
640x480157fps on Radeon 4650... Now is 380 fps yes compared
That looks fine to me.
Thanks!
On 02/09/2016 04:58 AM, Michael Ellerman wrote:
On Mon, 2015-23-11 at 15:01:15 UTC, Douglas Miller wrote:
Add 'P' command with optional task_struct address to dump all/one task's
information: task pointer, kernel stack pointer, PID, PPID, state
(interpreted), CP
Hi,
I am trying to rebuild the kernel for one of our powerpc devices to include
kdump capture kernel functionality, but I'm having trouble getting it to load
for use on panic.
I'm running Linux 3.14.60 on e500v2 (COMX-P2020 module).
I've tried following the documentation at
https://www.kernel.
We finally got the chance to test it end of last week. I forgot to
update everyone Monday. B all appearances, the patch fixes the problem.
We did not see any new issues with the patch (vs. same test scenarios
without).
I'll also update the bugzilla.
Thanks,
Doug
On 02/08/2016 07:37 PM, Alexe
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
topic/math-emu
head: 0d351023a638b7c82abdd8d66ebf5b5b3d6cb169
commit: 3b76bfd2f01f3b9101f040878e2636cdb7f3bbdd [6/9] sh/math-emu: Move sh
from math-emu-old to math-emu
config: sh-allyesconfig (attached as .config)
reprodu
Le 08/02/2016 04:02, Stewart Smith a écrit :
Frederic Barrat writes:
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -183,7 +183,7 @@ Description:read only
Identifies the revision level of the PSL.
Users:
Le 09/02/2016 11:23, Christophe Leroy a écrit :
The main purpose of this patchset is to dramatically reduce the time
spent in DTLB miss handler. This is achieved by:
1/ Mapping RAM with 8M pages
2/ Mapping IMMR with a fixed 512K page
Change in v7:
* Don't include x_block_mapped() from compila
The main purpose of this patchset is to dramatically reduce the time
spent in DTLB miss handler. This is achieved by:
1/ Mapping RAM with 8M pages
2/ Mapping IMMR with a fixed 512K page
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we ge
We are spending between 40 and 160 cycles with a mean of 65 cycles in
the DTLB handling routine (measured with mftbl) so make it more
simple althought it adds one instruction.
With this modification, we get three registers available at all time,
which will help with following patch.
Signed-off-by:
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTL
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documenta
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19 --
The fixmap related functions try to map kernel pages that are
already mapped through Large TLBs. pte_offset_kernel() has to
return NULL for LTLBs, otherwise the caller will try to access
level 2 table which doesn't exist
Signed-off-by: Christophe Leroy
---
v3: new
v4: no change
v5: no change
v6:
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, and are never defined at the same time.
So rename them x_block_mapped() and define them in the relevant
places
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Functions are mutually exclusive so renamed iaw Scott co
Once the linear memory space has been mapped with 8Mb pages, as
seen in the related commit, we get 11 millions DTLB missed during
the reference 600s period. 77% of the misses are on user addresses
and 23% are on kernel addresses (1 fourth for linear address space
and 3 fourth for virtual address sp
On recent kernels, with some debug options like for instance
CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough
the kernel code fits in the first 8M.
Today, it is necessary to activate CONFIG_PIN_TLB to get more than 8M
at startup, allthough pinning TLB is not necessary for that.
This
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/mm/init_
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy
---
v2: no change
v3: fix comment as well
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/nohash/32/pgtable.h | 2 +-
arch/powerpc/mm/mmu_decl.h |
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xf000 : fixmap
* 0xfde0..0xfe00 : consistent mem
* 0xfddf6000..0xfde0 : early ioremap
* 0xc900..0xfddf6000
Add missing SPRN defines into reg_8xx.h
Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in
reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h
to have it self sufficient, as includers of reg_8xx.h don't all
include asm/page.h
Signed-off-by: Christophe Leroy
---
v2:
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
IMMR is now mapped by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/Kconfig
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/he
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no chan
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no ch
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff --
clear_pages() is never used expect by clear_page, and PPC32 is the
only architecture (still) having this function. Neither PPC64 nor
any other architecture has it.
This patch removes clear_pages() and moves clear_page() function
inline (same as PPC64) as it only is a few isns
Signed-off-by: Chris
flush/clean/invalidate _dcache_range() functions are all very
similar and are quite short. They are mainly used in __dma_sync()
perf_event locate them in the top 3 consumming functions during
heavy ethernet activity
They are good candidate for inlining, as __dma_sync() does
almost nothing but call
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 i
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2 inse
Remove one instruction in mulhdu
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/kernel/misc_32.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/p
Yeah, I can see how that is confusing. Since, all three possible valid
crq message types have the first bit set I think this was originally a
cute hack to grab anything that was likely valid. Then in
ibmvscsi_handle_crq() we explicitly match the full header value in a
switch statement logging anyt
On 02/09/2016 09:41 AM, Manoj Kumar wrote:
>> Yeah, I can see how that is confusing. Since, all three possible valid
>> crq message types have the first bit set I think this was originally a
>> cute hack to grab anything that was likely valid. Then in
>> ibmvscsi_handle_crq() we explicitly match th
Hi Alan,
Your patch for "powerpc: Simplify module TOC handling" is causing the
Fedora ppc64le to fail to build with depmod failures. Reverting the
commit fixes it for us on rawhide.
We're getting the out put below, full logs at [1]. Let me know if you
have any other queries.
Regards,
Peter
[1]
On 02/09/2016 04:36 AM, Michael Ellerman wrote:
On Tue, 2016-02-09 at 00:38 -0500, David Long wrote:
From: "David A. Long"
Move duplicate and functionally equivalent code for accessing registers
and stack (CONFIG_HAVE_REGS_AND_STACK_ACCESS_API) from arch subdirs into
common kernel files.
I'm
On 02/09/2016 04:45 AM, Ingo Molnar wrote:
* Michael Ellerman wrote:
On Tue, 2016-02-09 at 00:38 -0500, David Long wrote:
From: "David A. Long"
Move duplicate and functionally equivalent code for accessing registers
and stack (CONFIG_HAVE_REGS_AND_STACK_ACCESS_API) from arch subdirs into
On Tue, Feb 9, 2016 at 5:28 PM, Peter Robinson wrote:
> Hi Alan,
>
> Your patch for "powerpc: Simplify module TOC handling" is causing the
> Fedora ppc64le to fail to build with depmod failures. Reverting the
> commit fixes it for us on rawhide.
Anton's patch [1] fixes it.
[1]
https://build.open
On Tue, 2016-02-09 at 22:02 +0100, Dinar Valeev wrote:
> On Tue, Feb 9, 2016 at 5:28 PM, Peter Robinson wrote:
> > Hi Alan,
> >
> > Your patch for "powerpc: Simplify module TOC handling" is causing the
> > Fedora ppc64le to fail to build with depmod failures. Reverting the
> > commit fixes it fo
On 02/10/2016 01:28 AM, Douglas Miller wrote:
We finally got the chance to test it end of last week. I forgot to update
everyone Monday. B all appearances, the patch fixes the problem. We did not
see any new issues with the patch (vs. same test scenarios without).
I'll also update the bugzilla.
On Mon, 2016-01-25 at 16:31 +0100, Torsten Duwe wrote:
> This patch complements the "notrace" attribute for selected functions.
> It adds -mprofile-kernel to the cc flags to be stripped from the command
> line for code-patching.o and feature-fixups.o, in addition to "-pg"
This could probably be f
On Mon, 2016-01-25 at 16:31 +0100, Torsten Duwe wrote:
> At least POWER7/8 have MMUs that don't completely autoload;
> a normal, recoverable memory fault might pass through these functions.
> If a dynamic tracer function causes such a fault, any of these functions
> being traced with -mprofile-ker
Michael Ellerman [m...@ellerman.id.au] wrote:
> Here you read from bytes[i] where i can be > 1 (AFAICS).
Yes, buffer is large enough and I thought this construct of
array was used in a several places. Maybe they are being
changed out now (struct pid has one such usage).
>
> That's fishy at best,
From f1afe08fbc9797ff63adf03efe564a807a37cfe6 Mon Sep 17 00:00:00 2001
From: Sukadev Bhattiprolu
Date: Tue, 9 Feb 2016 02:47:45 -0500
Subject: [PATCH V2 1/1] powerpc/perf/hv-gpci: Increase request buffer size
The GPCI hcall allows for a 4K buffer but we limit the buffer to 1K.
The problem with a
From: Wei Yang
This adds weak function pcibios_bus_add_device() for arch dependent
code could do proper setup. For example, powerpc could setup EEH
related resources for SRIOV VFs.
Signed-off-by: Wei Yang
Reviewed-by: Gavin Shan
Acked-by: Bjorn Helgaas
---
drivers/pci/bus.c | 3 +++
includ
From: Wei Yang
During EEH recovery, hotplug is applied to the devices which don't
have drivers or their drivers don't support EEH. However, the hotplug,
which was implemented based on PCI bus, can't be applied to VF directly.
Instead, we unplug and plug individual PCI devices (VFs).
This renames
From: Wei Yang
After PE reset, OPAL API opal_pci_reinit() is called on all devices
contained in the PE to reinitialize them. While skiboot is not aware of
VFs, we have to implement the function in kernel to reinitialize VFs after
reset on PE for VFs.
In this patch, two functions pnv_pci_fixup_vf
From: Wei Yang
VFs and their corresponding pdn are created and released dynamically
when their PF's SRIOV capability is enabled and disabled. This creates
and releases EEH devices for VFs when creating and releasing their pdn
instances, which means EEH devices and pdn instances have same life
cyc
From: Wei Yang
This restricts the EEH address cache to use only the first 7 BARs. This
makes __eeh_addr_cache_insert_dev() ignore PCI bridge window and IOV BARs.
As the result of this change, eeh_addr_cache_get_dev() will return VFs from
VF's resource addresses instead of parent PFs.
This also r
From: Wei Yang
PEs for VFs don't have primary bus. So they have to have their own reset
backend, which is used during EEH recovery. The patch implements the reset
backend for VF's PE by issuing FLR or AF FLR to the VFs, which are contained
in the PE.
Signed-off-by: Wei Yang
Acked-by: Gavin Shan
From: Wei Yang
This creates PEs for VFs in the weak function pcibios_bus_add_device().
Those PEs for VFs are identified with newly introduced flag EEH_PE_VF
so that we treat them differently during EEH recovery.
Signed-off-by: Wei Yang
Acked-by: Gavin Shan
---
arch/powerpc/include/asm/eeh.h
This applies to linux-powerpc-next and additional unmerged patches:
[v2,1/4] powerpc/eeh: Fix stale cached primary bus
powerpc/eeh: fix incorrect function name in comment
[V2] powerpc/powernv: Remove support for p5ioc2
[V7,1/6] powerpc/powernv: don't enable SRIOV when VF BAR has non
64bit-prefetc
From: Wei Yang
As commit ac205b7bb72f ("PCI: make sriov work with hotplug remove")
indicates, VFs which is on the same PCI bus as their PF, should be
removed before the PF. Otherwise, we might run into kernel crash
at PCI unplugging time.
This applies the above pattern to powerpc PCI hotplug pat
From: Wei Yang
PFs are enumerated on PCI bus, while VFs are created by PF's driver.
In EEH recovery, it has two cases:
1. Device and driver is EEH aware, error handlers are called.
2. Device and driver is not EEH aware, un-plug the device and plug it again
by enumerating it.
The special thing h
Excerpts from Frederic Barrat's message of 2016-02-10 02:21:19 +1100:
>
> Le 08/02/2016 04:02, Stewart Smith a écrit :
> > Frederic Barrat writes:
> >> --- a/Documentation/ABI/testing/sysfs-class-cxl
> >> +++ b/Documentation/ABI/testing/sysfs-class-cxl
> >> @@ -183,7 +183,7 @@ Description:rea
Acked-by: Ian Munsie
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Acked-by: Ian Munsie
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Excerpts from Frederic Barrat's message of 2016-02-07 00:28:50 +1100:
> Cxl kernel API was defining the process problem state area during
> context initialization, making it possible to map the problem state
> area before attaching the context. This won't work on a powerVM
> guest. So do the logica
Acked-by: Ian Munsie
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Excerpts from Frederic Barrat's message of 2016-02-07 00:28:52 +1100:
> Rename a few functions, mostly prefixed by 'cxl_', to make clear that
> the implementation is 'bare-metal' specific.
Patch looks fine to me, though the commit message should probably say
that you are changing the 'cxl_' prefix
Acked-by: Ian Munsie
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> The context parameter when calling cxl_irq() should be strongly typed.
Fair enough ;-)
Acked-by: Ian Munsie
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PAGE_EXEC is required for inittext, otherwise CONFIG_DEBUG_PAGEALLOC
ends up with an Oops
[0.00] Inode-cache hash table entries: 8192 (order: 1, 32768 bytes)
[0.00] Sorting __ex_table...
[0.00] bootmem::free_all_bootmem_core nid=0 start=0 end=2000
[0.00] Unable to h
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