[PATCH 01/31] scatterlist: add sg_pfn and sg_has_page helpers

Signed-off-by: Christoph Hellwig --- include/linux/scatterlist.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h index 9b1ef0c..b1056bf 100644 --- a/include/linux/scatterlist.h +++ b/include/linux/scatterlist.h @@ -230,6 +2

[PATCH 02/31] scatterlist: use sg_phys()

From: Dan Williams Coccinelle cleanup to replace open coded sg to physical address translations. This is in preparation for introducing scatterlists that reference __pfn_t. // sg_phys.cocci: convert usage page_to_phys(sg_page(sg)) to sg_phys(sg) // usage: make coccicheck COCCI=sg_phys.cocci MOD

[PATCH 04/31] x86/pci-nommu: handle page-less SG entries

Just remove a BUG_ON, the code handles them just fine as-is. Signed-off-by: Christoph Hellwig --- arch/x86/kernel/pci-nommu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kernel/pci-nommu.c b/arch/x86/kernel/pci-nommu.c index da15918..a218059 100644 --- a/arch/x86/kernel/pci-nommu

[PATCH 03/31] dma-debug: handle page-less SG entries

Use sg_pfn to get a the PFN and skip checks that require a kernel virtual address. Signed-off-by: Christoph Hellwig --- lib/dma-debug.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/dma-debug.c b/lib/dma-debug.c index dace71f..a215a80 100644 --- a/lib/dma-deb

RFC: prepare for struct scatterlist entries without page backing

Dan Williams started to look into addressing I/O to and from Persistent Memory in his series from June: http://thread.gmane.org/gmane.linux.kernel.cross-arch/27944 I've started looking into DMA mapping of these SGLs specifically instead of the map_pfn method in there. In addition to supp

[PATCH 05/31] x86/pci-calgary: handle page-less SG entries

For the iommu offset we just need and offset into the page. Calculate that using the physical address instead of using the virtual address so that we don't require a virtual mapping. Signed-off-by: Christoph Hellwig --- arch/x86/kernel/pci-calgary_64.c | 10 -- 1 file changed, 4 inserti

[PATCH 06/31] alpha/pci-noop: handle page-less SG entries

Use sg_phys() instead of virt_to_phys(sg_virt(sg)) so that we don't require a kernel virtual address. Signed-off-by: Christoph Hellwig --- arch/alpha/kernel/pci-noop.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-no

[PATCH 07/31] alpha/pci_iommu: handle page-less SG entries

Use sg_phys() instead of virt_to_phys(sg_virt(sg)) so that we don't require a kernel virtual address, and switch a few debug printfs to print physical instead of virtual addresses. Signed-off-by: Christoph Hellwig --- arch/alpha/kernel/pci_iommu.c | 36 +++- 1 fil

[PATCH 08/31] c6x: handle page-less SG entries

Use sg_phys() instead of virt_to_phys(sg_virt(sg)) so that we don't require a kernel virtual address. Signed-off-by: Christoph Hellwig --- arch/c6x/kernel/dma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/c6x/kernel/dma.c b/arch/c6x/kernel/dma.c index ab7b12d..79ca

[PATCH 09/31] ia64/pci_dma: handle page-less SG entries

Use sg_phys() instead of virt_to_phys(sg_virt(sg)) so that we don't require a kernel virtual address. Signed-off-by: Christoph Hellwig --- arch/ia64/sn/pci/pci_dma.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c in

[PATCH 10/31] powerpc/iommu: handle page-less SG entries

For the iommu offset we just need and offset into the page. Calculate that using the physical address instead of using the virtual address so that we don't require a virtual mapping. Signed-off-by: Christoph Hellwig --- arch/powerpc/kernel/iommu.c | 14 +++--- 1 file changed, 7 insertio

[PATCH 11/31] sparc/iommu: handle page-less SG entries

Use sg_phys() instead of __pa(sg_virt(sg)) so that we don't require a kernel virtual address. Signed-off-by: Christoph Hellwig --- arch/sparc/kernel/iommu.c| 2 +- arch/sparc/kernel/iommu_common.h | 4 +--- arch/sparc/kernel/pci_sun4v.c| 2 +- 3 files changed, 3 insertions(+), 5 dele

[PATCH 12/31] mn10300: handle page-less SG entries

Just remove a BUG_ON, the code handles them just fine as-is. Signed-off-by: Christoph Hellwig --- arch/mn10300/include/asm/dma-mapping.h | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/mn10300/include/asm/dma-mapping.h b/arch/mn10300/include/asm/dma-mapping.h index

[PATCH 13/31] sparc/ldc: handle page-less SG entries

Use sg_phys(sg) & PAGE_MASK instead of page_to_pfn(sg_page(sg)) << PAGE_SHIFT to get at the page-aligned physical address ofa SG entry, so that we don't require a page backing for SG entries. Signed-off-by: Christoph Hellwig --- arch/sparc/kernel/ldc.c | 4 ++-- 1 file changed, 2 ins

[PATCH 14/31] sparc32/io-unit: handle page-less SG entries

For the iommu offset we just need and offset into the page. Calculate that using the physical address instead of using the virtual address so that we don't require a virtual mapping. Signed-off-by: Christoph Hellwig --- arch/sparc/mm/io-unit.c | 23 --- 1 file changed, 12 in

[PATCH 15/31] sparc32/iommu: handle page-less SG entries

Pass a PFN to iommu_get_one instad of calculating it locall from a page structure so that we don't need pages for every address we can DMA to or from. Also further restrict the cache flushing as we now have a non-highmem way of not kernel virtual mapped physical addresses. Signed-off-by: Christop

[PATCH 16/31] s390: handle page-less SG entries

Use sg_phys() instead of page_to_phys(sg_page(sg)) so that we don't require a page structure for all DMA memory. Signed-off-by: Christoph Hellwig --- arch/s390/pci/pci_dma.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/s390/pci/pci_dma.c b/arch/s

[PATCH 17/31] ia64/sba_iommu: remove sba_sg_address

Signed-off-by: Christoph Hellwig --- arch/ia64/hp/common/sba_iommu.c | 22 ++ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c index 344387a..9e5aa8e 100644 --- a/arch/ia64/hp/common/sba_iommu.c +

[PATCH 18/31] nios2: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page() and use sg_phys to get the physical address directly. Signed-off-by: Christoph Hellwig --- arch/nios2/mm/dma-mapping.c | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/nios2/mm/dma-ma

[PATCH 19/31] arc: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page() and use sg_phys to get the physical address directly. Signed-off-by: Christoph Hellwig --- arch/arc/include/asm/dma-mapping.h | 26 +++--- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/arch/arc/include/

[PATCH 20/31] avr32: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page() and use sg_phys to get the physical address directly, bypassing the noop page_to_bus. Signed-off-by: Christoph Hellwig --- arch/avr32/include/asm/dma-mapping.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --gi

[PATCH 21/31] blackfin: handle page-less SG entries

Switch from sg_virt to sg_phys as blackfin like all nommu architectures has a 1:1 virtual to physical mapping. Signed-off-by: Christoph Hellwig --- arch/blackfin/kernel/dma-mapping.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/blackfin/kernel/dma-mapping.c b/arc

[PATCH 22/31] metag: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page(). Signed-off-by: Christoph Hellwig --- arch/metag/include/asm/dma-mapping.h | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/metag/include/asm/dma-mapping.h b/arch/metag/include/asm/dma-mapp

[PATCH 23/31] sh: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page(). Signed-off-by: Christoph Hellwig --- arch/sh/kernel/dma-nommu.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/sh/kernel/dma-nommu.c b/arch/sh/kernel/dma-nommu.c index 5b0bfcd..3b64dc7 100644 --- a/ar

[PATCH 24/31] xtensa: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page(). Signed-off-by: Christoph Hellwig --- arch/xtensa/include/asm/dma-mapping.h | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/xtensa/include/asm/dma-mapping.h b/arch/xtensa/include/asm/dma-mapping

[PATCH 25/31] frv: handle page-less SG entries

Only call kmap_atomic_primary when the SG entry is mapped into kernel virtual space. XXX: the code already looks odd due to the lack of pairing between kmap_atomic_primary and kunmap_atomic_primary. Does it work either before or after this patch? Signed-off-by: Christoph Hellwig --- arch/frv/m

[PATCH 26/31] openrisc: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page() and use sg_phys to get the physical address directly. Signed-off-by: Christoph Hellwig --- arch/openrisc/kernel/dma.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/k

[PATCH 27/31] mips: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page() and use sg_phys to get the physical address directly. To do this consolidate the two platform callouts using pages and virtual addresses into a single one using a physical address. Signed-off-by: Christoph Hellwig --- arch/mips/bmips/dma.

[PATCH 28/31] powerpc: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page(). Signed-off-by: Christoph Hellwig --- arch/powerpc/kernel/dma.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c index 35e4dcc..cece40b 100644 --- a/arch/p

[PATCH 29/31] parisc: handle page-less SG entries

Make all cache invalidation conditional on sg_has_page() and use sg_phys to get the physical address directly. Signed-off-by: Christoph Hellwig --- arch/parisc/kernel/pci-dma.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/parisc/kernel/

[PATCH 30/31] intel-iommu: handle page-less SG entries

Just remove a BUG_ON, the code handles them just fine as-is. Signed-off-by: Christoph Hellwig --- drivers/iommu/intel-iommu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 3541d65..ae10573 100644 --- a/drivers/iommu/intel-iommu

[PATCH 31/31] dma-mapping-common: skip kmemleak checks for page-less SG entries

Signed-off-by: Christoph Hellwig --- include/asm-generic/dma-mapping-common.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/asm-generic/dma-mapping-common.h b/include/asm-generic/dma-mapping-common.h index 940d5ec..afc3eaf 100644 --- a/include/asm-generic/dma-

Re: [PATCH] powerpc/xmon: Allow limiting the size of the paca display

On 08/12/2015 12:27 PM, Michael Ellerman wrote: > The paca display is already more than 24 lines, which can be problematic > if you have an old school 80x24 terminal, or more likely you are on a > virtual terminal which does not scroll for whatever reason. > > We'd like to expand the paca display

Re: [V3] powerpc/irq: Enable some more exceptions in /proc/interrupts interface

On 08/09/2015 07:57 AM, Benjamin Herrenschmidt wrote: > On Tue, 2015-08-04 at 19:57 +1000, Michael Ellerman wrote: >> > On Mon, 2015-13-07 at 08:16:06 UTC, Anshuman Khandual wrote: >>> > > This patch enables facility unavailable exceptions for generic facility, >>> > > FPU, ALTIVEC and VSX in /proc

Re: [PATCH 09/10] Define PERF_PMU_TXN_READ interface

On Tue, Aug 11, 2015 at 09:14:00PM -0700, Sukadev Bhattiprolu wrote: > | +static void __perf_read_group_add(struct perf_event *leader, u64 > read_format, u64 *values) > | { > | + struct perf_event *sub; > | + int n = 1; /* skip @nr */ > > This n = 1 is to skip over the values[0] = 1 + nr_sib

Re: [PATCH v7 2/6] mm: mlock: Add new mlock system call

On Sun 09-08-15 01:22:52, Eric B Munson wrote: > With the refactored mlock code, introduce a new system call for mlock. > The new call will allow the user to specify what lock states are being > added. mlock2 is trivial at the moment, but a follow on patch will add > a new mlock state making it us

Re: [PATCH] powerpc/xmon: Allow limiting the size of the paca display

On Wed, 2015-08-12 at 13:24 +0530, Anshuman Khandual wrote: > On 08/12/2015 12:27 PM, Michael Ellerman wrote: > > @@ -2090,9 +2092,12 @@ static void dump_one_paca(int cpu) > > printf(" %-*s = %s\n", 16, "present", cpu_present(cpu) ? "yes" : "no"); > > printf(" %-*s = %s\n", 16, "online", cp

Re: [PATCH 30/31] intel-iommu: handle page-less SG entries

On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote: > Just remove a BUG_ON, the code handles them just fine as-is. > > Signed-off-by: Christoph Hellwig Acked-by: David Woodhouse -- David WoodhouseOpen Source Technology Centre david.woodho...@intel.com

Re: [PATCH 20/31] avr32: handle page-less SG entries

Around Wed 12 Aug 2015 09:05:39 +0200 or thereabout, Christoph Hellwig wrote: > Make all cache invalidation conditional on sg_has_page() and use > sg_phys to get the physical address directly, bypassing the noop > page_to_bus. > > Signed-off-by: Christoph Hellwig Acked-by: Hans-Christian Egtvedt

RE: [PATCH v2 05/10] cxl: Refactor adaptor init/teardown

From: Cyril Bur > Sent: 11 August 2015 07:01 ... > You have a dilema with the use of ugly if (rc = foo()). I don't like it but > the > file is littered with it. > > Looks like the majority of uses in this file the conditional block is only > one line then it makes sense (or at least in terms of n

Re: [PATCH 19/31] arc: handle page-less SG entries

On Wednesday 12 August 2015 12:39 PM, Christoph Hellwig wrote: > Make all cache invalidation conditional on sg_has_page() and use > sg_phys to get the physical address directly. > > Signed-off-by: Christoph Hellwig With a minor nit below. Acked-by: Vineet Gupta > --- > arch/arc/include/asm/dm

Re: [PATCH v6 05/42] powerpc/powernv: Track IO/M32/M64 segments from PE

On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote: >On 08/11/2015 10:03 AM, Gavin Shan wrote: >>On Mon, Aug 10, 2015 at 05:16:40PM +1000, Alexey Kardashevskiy wrote: >>>On 08/06/2015 02:11 PM, Gavin Shan wrote: The patch is adding 6 bitmaps, three to PE and three to PHB, to t

Re: [PATCH v6 03/42] powerpc/powernv: Enable M64 on P7IOC

On Tue, Aug 11, 2015 at 12:06:26PM +1000, Alexey Kardashevskiy wrote: >On 08/11/2015 09:45 AM, Gavin Shan wrote: >>On Mon, Aug 10, 2015 at 04:30:09PM +1000, Alexey Kardashevskiy wrote: >>>On 08/06/2015 02:11 PM, Gavin Shan wrote: The patch enables M64 window on P7IOC, which has been enabled on

Re: [PATCH v6 05/42] powerpc/powernv: Track IO/M32/M64 segments from PE

On 08/12/2015 08:45 PM, Gavin Shan wrote: On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote: On 08/11/2015 10:03 AM, Gavin Shan wrote: On Mon, Aug 10, 2015 at 05:16:40PM +1000, Alexey Kardashevskiy wrote: On 08/06/2015 02:11 PM, Gavin Shan wrote: The patch is adding 6 bitma

Re: [PATCH v6 05/42] powerpc/powernv: Track IO/M32/M64 segments from PE

On Wed, Aug 12, 2015 at 09:05:09PM +1000, Alexey Kardashevskiy wrote: >On 08/12/2015 08:45 PM, Gavin Shan wrote: >>On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote: >>>On 08/11/2015 10:03 AM, Gavin Shan wrote: On Mon, Aug 10, 2015 at 05:16:40PM +1000, Alexey Kardashevskiy wr

Re: [PATCH 16/31] s390: handle page-less SG entries

On Wed, 12 Aug 2015, Christoph Hellwig wrote: > Use sg_phys() instead of page_to_phys(sg_page(sg)) so that we don't > require a page structure for all DMA memory. > > Signed-off-by: Christoph Hellwig Acked-by: Sebastian Ott > --- > arch/s390/pci/pci_dma.c | 20 ++-- > 1 file

[PATCH v2] powerpc/xmon: Allow limiting the size of the paca display

The paca display is already more than 24 lines, which can be problematic if you have an old school 80x24 terminal, or more likely you are on a virtual terminal which does not scroll for whatever reason. We'd like to expand the paca display even more, so add a way to limit the number of lines that

Re: [PATCH v6 05/42] powerpc/powernv: Track IO/M32/M64 segments from PE

On 08/12/2015 09:20 PM, Gavin Shan wrote: On Wed, Aug 12, 2015 at 09:05:09PM +1000, Alexey Kardashevskiy wrote: On 08/12/2015 08:45 PM, Gavin Shan wrote: On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote: On 08/11/2015 10:03 AM, Gavin Shan wrote: On Mon, Aug 10, 2015 at 05:

[PATCH 01/20] powerpc/8xx: Save r3 all the time in DTLB miss handler

We are spending between 40 and 160 cycles with a mean of 65 cycles in the TLB handling routines (measured with mftbl) so make it more simple althought it adds one instruction. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 13 - 1 file changed, 4 insertions(+),

[PATCH 00/20] powerpc/8xx: Use large pages for RAM and IMMR and other improvments.

The main purpose of this patchset is to dramatically reduce the time spent in DTLB miss handler. This is achieved by: 1/ Mapping RAM with 8M pages 2/ Mapping IMMR with a fixed 512K page On a live running system (VoIP gateway for Air Trafic Control), over a 10 minutes period (with 277s idle), we ge

[PATCH 02/20] powerpc/8xx: Map linear kernel RAM with 8M pages

On a live running system (VoIP gateway for Air Trafic Control), over a 10 minutes period (with 277s idle), we get 87 millions DTLB misses and approximatly 35 secondes are spent in DTLB handler. This represents 5.8% of the overall time and even 10.8% of the non-idle time. Among those 87 millions DTL

[PATCH 03/20] powerpc: Update documentation for noltlbs kernel parameter

Now the noltlbs kernel parameter is also applicable to PPC8xx Signed-off-by: Christophe Leroy --- Documentation/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index ca80921..572d

[PATCH 04/20] powerpc/8xx: move setup_initial_memory_limit() into 8xx_mmu.c

Now we have a 8xx specific .c file for that so put it in there as other powerpc variants do Signed-off-by: Christophe Leroy --- arch/powerpc/mm/8xx_mmu.c | 17 + arch/powerpc/mm/init_32.c | 19 --- 2 files changed, 17 insertions(+), 19 deletions(-) diff --git a/a

[PATCH 05/20] powerpc/8xx: Fix vaddr for IMMR early remap

Memory: 124428K/131072K available (3748K kernel code, 188K rwdata, 648K rodata, 508K init, 290K bss, 6644K reserved) Kernel virtual memory layout: * 0xfffdf000..0xf000 : fixmap * 0xfde0..0xfe00 : consistent mem * 0xfddf6000..0xfde0 : early ioremap * 0xc900..0xfddf6000

[PATCH 06/20] powerpc32: iounmap() cannot vunmap() area mapped by TLBCAMs either

iounmap() cannot vunmap() area mapped by TLBCAMs either Signed-off-by: Christophe Leroy --- arch/powerpc/mm/pgtable_32.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c index 7692d1b..03a073a 100644 --- a/arch/pow

[PATCH 07/20] powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together

x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of purpose, so lets group them into a single function. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/pgtable_32.c | 33 ++--- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/powe

[PATCH 08/20] powerpc/8xx: Map IMMR area with 512k page at a fixed address

Once the linear memory space has been mapped with 8Mb pages, as seen in the related commit, we get 11 millions DTLB missed during the reference 600s period. 77% of the missed are on user addresses and 23% are on kernel addresses (1 fourth for linear address space and 3 fourth for virtual address sp

[PATCH 09/20] powerpc/8xx: show IMMR area in startup memory layout

show IMMR area in startup memory layout Signed-off-by: Christophe Leroy --- arch/powerpc/mm/mem.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index e1fe333..f987321 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c @@ -367,6

[PATCH 10/20] powerpc/8xx: CONFIG_PIN_TLB unneeded for CONFIG_PPC_EARLY_DEBUG_CPM

IMMR is now mapped at 0xff00 by page tables so it is not anymore necessary to PIN TLBs Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig.debug | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index 70168a2..452b086 100644 --- a

[PATCH 11/20] powerpc/8xx: map 16M RAM at startup

On recent kernels, with some debug options like for instance CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough the kernel code fits in the first 8M. Today, it is necessary to activate CONFIG_PIN_TLB to get more than 8M at startup, allthough pinning TLB is not necessary for that. This

[PATCH 12/20] powerpc/8xx: move 8xx SPRN defines into reg_8xx.h and add some missing ones

Move 8xx SPRN defines into reg_8xx.h and add some missing ones Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/mmu-8xx.h | 26 +- arch/powerpc/include/asm/reg_8xx.h | 24 2 files changed, 37 insertions(+), 13 deletions(-) diff --git

[PATCH 13/20] powerpc/8xx: Handle CPU6 ERRATA directly in mtspr() macro

MPC8xx has an ERRATA on the use of mtspr() for some registers This patch includes the ERRATA handling directly into mtspr() macro so that mtspr() users don't need to bother about that errata Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/reg.h | 2 + arch/powerpc/include/asm/r

[PATCH 14/20] powerpc/8xx: remove special handling of CPU6 errata in set_dec()

CPU6 ERRATA is now handled directly in mtspr(), so we can use the standard set_dec() fonction in all cases. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/time.h | 6 +- arch/powerpc/kernel/head_8xx.S | 18 -- 2 files changed, 1 insertion(+), 23 deletions(-)

[PATCH 15/20] powerpc/8xx: rewrite set_context() in C

There is no real need to have set_context() in assembly. Now that we have mtspr() handling CPU6 ERRATA directly, we can rewrite set_context() in C language for easier maintenance. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 44 --

[PATCH 16/20] powerpc/8xx: rewrite flush_instruction_cache() in C

On PPC8xx, flushing instruction cache is performed by writing in register SPRN_IC_CST. This registers suffers CPU6 ERRATA. The patch rewrites the fonction in C so that CPU6 ERRATA will be handled transparently Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/misc_32.S | 10 -- arc

[PATCH 17/20] powerpc32: Remove clear_pages()

clear_pages() is never used, and PPC32 is the only architecture (still) having this function. Neither PPC64 nor any other architecture has it. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/page_32.h | 3 +-- arch/powerpc/kernel/misc_32.S | 7 +++ arch/powerpc/kernel/ppc_k

[PATCH 18/20] powerpc32: Remove useless/wrong MMU:setio progress message

Commit 771168494719 ("[POWERPC] Remove unused machine call outs") removed the call to setup_io_mappings(), so remove the associated progress line message Signed-off-by: Christophe Leroy --- arch/powerpc/mm/init_32.c | 4 1 file changed, 4 deletions(-) diff --git a/arch/powerpc/mm/init_32.c

[PATCH 19/20] powerpc/8xx: also use r3 in the ITLB miss in all situations

We are spending between 40 and 160 cycles with a mean of 65 cycles in the TLB handling routines (measured with mftbl) so make it more simple althought it adds one instruction Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 15 --- 1 file changed, 4 insertions(+),

[PATCH 20/20] powerpc32: remove ioremap_base

ioremap_base is not initialised and is nowhere used so remove it Signed-off-by: Christophe Leroy --- arch/powerpc/mm/mmu_decl.h | 1 - arch/powerpc/mm/pgtable_32.c| 1 - arch/powerpc/platforms/embedded6xx/mpc10x.h | 8 3 files changed, 10 deletions(-) d

Re: RFC: prepare for struct scatterlist entries without page backing

On 08/12/2015 10:05 AM, Christoph Hellwig wrote: > Dan Williams started to look into addressing I/O to and from > Persistent Memory in his series from June: > > http://thread.gmane.org/gmane.linux.kernel.cross-arch/27944 > > I've started looking into DMA mapping of these SGLs specifically i

Re: [PATCH 29/31] parisc: handle page-less SG entries

On Wed, Aug 12, 2015 at 12:05 AM, Christoph Hellwig wrote: > Make all cache invalidation conditional on sg_has_page() and use > sg_phys to get the physical address directly. So this worries me a bit (I'm just reacting to one random patch in the series). The reason? I think this wants a big honk

Re: [PATCH 31/31] dma-mapping-common: skip kmemleak checks for page-less SG entries

On Wed, Aug 12, 2015 at 12:05 AM, Christoph Hellwig wrote: > + for_each_sg(sg, s, nents, i) { > + if (sg_has_page(s)) > + kmemcheck_mark_initialized(sg_virt(s), s->length); > + } [ Again, I'm responding to one random patch - this pattern was in othe

Re: RFC: prepare for struct scatterlist entries without page backing

On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote: > Dan Williams started to look into addressing I/O to and from > Persistent Memory in his series from June: > > http://thread.gmane.org/gmane.linux.kernel.cross-arch/27944 > > I've started looking into DMA mapping of these SGLs spe

Re: [PATCH v3 1/1] KVM: PPC: Book3S: correct width in XER handling

On 06.08.15 12:16, Laurent Vivier wrote: > Hi, > > I'd also like to see this patch in the mainstream as it fixes a bug > appearing when we switch from vCPU context to hypervisor context (guest > crash). Thanks, applied to kvm-ppc-queue. Alex ___ Lin

Re: [PATCH] kvm:powerpc:Fix incorrect return statement in the function mpic_set_default_irq_routing

On 07.08.15 17:54, Nicholas Krause wrote: > This fixes the incorrect return statement in the function > mpic_set_default_irq_routing from always returning zero > to signal success to this function's caller to instead > return the return value of kvm_set_irq_routing as this > function can fail and

Re: [PATCH] kvm:powerpc:Fix return statements for wrapper functions in the file book3s_64_mmu_hv.c

On 10.08.15 17:27, Nicholas Krause wrote: > This fixes the wrapper functions kvm_umap_hva_hv and the function > kvm_unmap_hav_range_hv to return the return value of the function > kvm_handle_hva or kvm_handle_hva_range that they are wrapped to > call internally rather then always making the calle

Re: [PATCH] kvm:powerpc:Fix incorrect return statement in the function mpic_set_default_irq_routing

On 2015-08-12 03:05 PM, Alexander Graf wrote: > > > On 07.08.15 17:54, Nicholas Krause wrote: >> This fixes the incorrect return statement in the function >> mpic_set_default_irq_routing from always returning zero >> to signal success to this function's caller to instead >> return the return va

Re: [PATCH] kvm:powerpc:Fix incorrect return statement in the function mpic_set_default_irq_routing

On 12.08.15 21:06, nick wrote: > > > On 2015-08-12 03:05 PM, Alexander Graf wrote: >> >> >> On 07.08.15 17:54, Nicholas Krause wrote: >>> This fixes the incorrect return statement in the function >>> mpic_set_default_irq_routing from always returning zero >>> to signal success to this function'

[v2 01/11] powerpc: re-add devm_ioremap_prot()

From: Emil Medve devm_ioremap_prot() was removed in commit dedd24a12, and was introduced in commit b41e5fffe8. This reverts commit dedd24a12fe6735898feeb06184ee346907abb5d. Signed-off-by: Emil Medve --- arch/powerpc/include/asm/io.h |3 +++ arch/powerpc/lib/Makefile |1 + arch/pow

[v2 00/11] Freescale DPAA QBMan Drivers

The Freescale Data Path Acceleration Architecture (DPAA) is a set of hardware components on specific QorIQ multicore processors. This architecture provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores and the accelerators. The

[v2 10/11] soc/qman: Add HOTPLUG_CPU support to the QMan driver

From: Hai-Ying Wang Add support for CPU hotplug for the DPAA 1.0 Queue Manager driver. Signed-off-by: Hai-Ying Wang Signed-off-by: Emil Medve Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/qman_portal.c | 43 +++ 1 file changed, 43 insertions(+) diff -

[v2 06/11] soc/qman: Add self-tester for QMan driver

From: Geoff Thorpe Add a self test for the DPAA 1.0 Queue Manager driver. The tests ensure that the driver can properly enqueue and dequeue from frame queues using the QMan portal infrastructure. Signed-off-by: Geoff Thorpe Signed-off-by: Emil Medve Signed-off-by: Roy Pledge --- drivers/soc/

[v2 05/11] soc/bman: Add self-tester for BMan driver

From: Geoff Thorpe Add a self test for the DPAA 1.0 Buffer Manager driver. This test ensures that the driver can properly acquire and release buffers using the BMan portal infrastructure. Signed-off-by: Geoff Thorpe Signed-off-by: Emil Medve Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbma

[v2 02/11] soc/fsl: Introduce DPAA BMan device management driver

From: Geoff Thorpe This driver enables the Freescale DPAA 1.0 Buffer Manager block. BMan is a hardware buffer pool manager that allows accelerators connected to the SoC datapath to acquire and release buffers during data processing. Signed-off-by: Geoff Thorpe Signed-off-by: Emil Medve Signed-

[v2 07/11] soc/bman: Add debugfs support for the BMan driver

From: Geoff Thorpe Add debugfs support for querying the state of hardware based Buffer Manager pools used in DPAA 1.0. Signed-off-by: Geoff Thorpe Signed-off-by: Emil Medve Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/Kconfig|7 ++ drivers/soc/fsl/qbman/Makefile |

[v2 09/11] soc/bman: Add HOTPLUG_CPU support to the BMan driver

From: Hai-Ying Wang Add support for CPU hotplug for the DPAA 1.0 Buffer Manager driver Signed-off-by: Hai-Ying Wang Signed-off-by: Emil Medve Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/bman_portal.c | 40 +++ drivers/soc/fsl/qbman/dpaa_sys.h|

[v2 08/11] soc/qman: Add debugfs support for the QMan driver

From: Geoff Thorpe Add debugfs sypport for querying the state of hardware based queues managed by the DPAA 1.0 Queue Manager. Signed-off-by: Geoff Thorpe Signed-off-by: Emil Medve Signed-off-by: Madalin Bucur Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/Makefile |1 + drive

[v2 11/11] soc/qman: add qman_delete_cgr_safe()

From: Madalin Bucur Add qman_delete_cgr_safe() that can be called from any CPU. This in turn schedules qman_delete_cgr() on the proper CPU. Signed-off-by: Madalin Bucur Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/qman_api.c | 46 ++ 1 file changed

Re: [PATCH 31/31] dma-mapping-common: skip kmemleak checks for page-less SG entries

Christoph, On 12 August 2015 at 08:05, Christoph Hellwig wrote: > Signed-off-by: Christoph Hellwig > --- > include/asm-generic/dma-mapping-common.h | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/include/asm-generic/dma-mapping-common.h > b/include/asm-generic/dm

Re: RFC: prepare for struct scatterlist entries without page backing

On Wed, Aug 12, 2015 at 10:00 AM, James Bottomley wrote: > On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote: ... >> However the ccio (parisc) and sba_iommu (parisc & ia64) IOMMUs seem >> to be operate mostly on virtual addresses. It's a fairly odd concept >> that I don't fully grasp, so

Re: [PATCH v2 05/10] cxl: Refactor adaptor init/teardown

> The function above doesn't even use the 'rc' value. Darn, you're right. I'll fix that in a new version. -- Regards, Daniel -- Regards, Daniel signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxp

Re: [PATCH v6 05/42] powerpc/powernv: Track IO/M32/M64 segments from PE

On Wed, Aug 12, 2015 at 10:57:33PM +1000, Alexey Kardashevskiy wrote: >On 08/12/2015 09:20 PM, Gavin Shan wrote: >>On Wed, Aug 12, 2015 at 09:05:09PM +1000, Alexey Kardashevskiy wrote: >>>On 08/12/2015 08:45 PM, Gavin Shan wrote: On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wr

Re: RFC: prepare for struct scatterlist entries without page backing

Hi, On Wed, Aug 12, 2015 at 10:42 PM, Boaz Harrosh wrote: > On 08/12/2015 10:05 AM, Christoph Hellwig wrote: >> It turns out most DMA mapping implementation can handle SGLs without >> page structures with some fairly simple mechanical work. Most of it >> is just about consistently using sg_phys.

Re: [PATCH v6 07/42] powerpc/powernv: Improve IO and M32 mapping

On Tue, Aug 11, 2015 at 12:32:13PM +1000, Alexey Kardashevskiy wrote: >On 08/11/2015 10:12 AM, Gavin Shan wrote: >>On Mon, Aug 10, 2015 at 05:40:08PM +1000, Alexey Kardashevskiy wrote: >>>On 08/06/2015 02:11 PM, Gavin Shan wrote: There're 3 windows (IO, M32 and M64) for PHB, root port and upstr

Re: [PATCH v6 08/42] powerpc/powernv: Calculate PHB's DMA weight dynamically

On Mon, Aug 10, 2015 at 07:21:12PM +1000, Alexey Kardashevskiy wrote: >On 08/06/2015 02:11 PM, Gavin Shan wrote: >>For P7IOC, the whole available DMA32 space, which is below the >>MEM32 space, is divided evenly into 256MB segments. The number >>of continuous segments assigned to one particular PE d

Re: [PATCH v6 10/42] powerpc/powernv: pnv_ioda_setup_dma() configure one PE only

On Tue, Aug 11, 2015 at 12:39:02PM +1000, Alexey Kardashevskiy wrote: >On 08/11/2015 10:29 AM, Gavin Shan wrote: >>On Mon, Aug 10, 2015 at 07:31:11PM +1000, Alexey Kardashevskiy wrote: >>>On 08/06/2015 02:11 PM, Gavin Shan wrote: The original implementation of pnv_ioda_setup_dma() iterates the

Re: [PATCH v6 11/42] powerpc/powernv: Trace DMA32 segments consumed by PE

On Mon, Aug 10, 2015 at 07:43:48PM +1000, Alexey Kardashevskiy wrote: >On 08/06/2015 02:11 PM, Gavin Shan wrote: >>On P7IOC, the whole DMA32 space is divided evenly to 256MB segments. >>Each PE can consume one or multiple DMA32 segments. Current code >>doesn't trace the available DMA32 segments and

Re: [PATCH v6 12/42] powerpc/powernv: Increase PE# capacity

On Tue, Aug 11, 2015 at 12:47:25PM +1000, Alexey Kardashevskiy wrote: >On 08/11/2015 10:38 AM, Gavin Shan wrote: >>On Mon, Aug 10, 2015 at 07:53:02PM +1000, Alexey Kardashevskiy wrote: >>>On 08/06/2015 02:11 PM, Gavin Shan wrote: Each PHB maintains an array helping to translate RID (Request >>>

Re: [PATCH v6 18/42] powerpc/powernv: Allocate PE# in deasending order

On Tue, Aug 11, 2015 at 12:50:33PM +1000, Alexey Kardashevskiy wrote: >On 08/11/2015 10:43 AM, Gavin Shan wrote: >>On Tue, Aug 11, 2015 at 12:39:02AM +1000, Alexey Kardashevskiy wrote: >>>On 08/06/2015 02:11 PM, Gavin Shan wrote: The available PE#, represented by a bitmap in the PHB, is allocat

Re: [PATCH v6 23/42] powerpc/powernv: Release PEs dynamically

On Tue, Aug 11, 2015 at 11:03:40PM +1000, Alexey Kardashevskiy wrote: >On 08/06/2015 02:11 PM, Gavin Shan wrote: >>This adds the refcount to PE, which represents number of PCI >>devices contained in the PE. When last device leaves from the >>PE, the PE together with its consumed resources (IO, DMA,

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