[...]
>> >
>> >Can you test this patch on imx SoC ?
>> >
>>
>> (Your email have some format issue.)
>
> Yeah missed to sent in plain text mode.
>
>>
>> I have tested this patch and it does not break imx SoC.
>> You can add my tag.
>> Tested-by: Dong Aisheng
>
> Thanks Dong !!
>
>>
>> However
On 8 June 2015 at 10:37, Ulf Hansson wrote:
> [...]
>
>>> >
>>> >Can you test this patch on imx SoC ?
>>> >
>>>
>>> (Your email have some format issue.)
>>
>> Yeah missed to sent in plain text mode.
>>
>>>
>>> I have tested this patch and it does not break imx SoC.
>>> You can add my tag.
>>>
Thanks a lot, Scott.
And now a patch was merged on git://git.linaro.org/people/ulf.hansson/mmc.git
next branch to fix this issue.
It should be no problem.
From 5fd26c7ecb32082745b0bd33c8e35badd1cb5a91 Mon Sep 17 00:00:00 2001
From: Ulf Hansson
Date: Fri, 5 Jun 2015 11:40:08 +0200
Subject: [PATC
From: Tang Yuantian
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback functi
From: "khand...@linux.vnet.ibm.com"
This patch enables privilege mode SW branch filters. Also modifies
POWER8 PMU branch filter configuration so that the privilege mode
branch filter implemented as part of base PMU event configuration
is reflected in bhrb filter mask. As a result, the SW will ski
This patch cleans up some existing indentation problem in code and
re organizes the BHRB processing code with an helper function named
'update_branch_entry' making it more readable. This patch does not
change any functionality.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-book3s.c
The kernel now supports SW based branch filters for book3s systems with
some specific requirements while dealing with HW supported branch filters
in order to achieve overall OR semantics prevailing in perf branch stack
sampling framework. This patch adapts the BHRB branch filter configuration
to me
Generic powerpc branch analysis support added in the code patching
library which will help the subsequent patch on SW based filtering
of branch records in perf.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/code-patching.h | 15
arch/powerpc/lib/code-patching.c |
This patch simply changes the name of the variable from 'bhrb_filter' to
'bhrb_hw_filter' in order to add one more variable which will track SW
filters in generic powerpc book3s code which will be implemented in the
subsequent patch. This patch does not change any functionality.
Signed-off-by: Ans
From: "khand...@linux.vnet.ibm.com"
This patch adds a test for verifying that all the branch stack
sampling filters supported on powerpc works correctly. It also
adds some assembly helper functions in this regard. This patch
extends the generic event description to handle kernel mapped
ring buffe
BHRB is a rolling buffer. Hence we might end up in a situation where
we have read one target address but when we try to read the next entry
indicating the from address of the targe, the buffer just overflows.
In this case, the captured from address will be zero which indicates
the end of the buffer
This patch does some code re-arrangements to make it clear that it ignores
any separate privilege level branch filter request and does not support
any combinations of HW PMU branch filters.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 22 +++---
1 file ch
This patch enables SW based post processing of BHRB captured branches
to be able to meet more user defined branch filtration criteria in perf
branch stack sampling framework. These changes increase the number of
branch filters and their valid combinations on any powerpc64 server
platform with BHRB
From: "khand...@linux.vnet.ibm.com"
'commit 9de5cb0f6df8 ("powerpc/perf: Add per-event excludes on Power8")'
broke the PMU based BHRB privilege level filter. BHRB depends on the
same MMCR0 bits for privilege level filter which was used to freeze all
the PMCs as a group. Once we moved to individua
On 06/05/2015 03:31 AM, Michael Ellerman wrote:
On Thu, 2015-04-06 at 12:03:17 UTC, Vipin K Parashar wrote:
This patch adds support for FSP (Flexible Service Processor)
EPOW (Early Power Off Warning) and DPO (Delayed Power Off) events for
the PowerNV platform. EPOW events are generated by FSP d
This patch adds support for FSP (Flexible Service Processor)
EPOW (Early Power Off Warning) and DPO (Delayed Power Off) events for
the PowerNV platform. EPOW events are generated by FSP due to various
critical system conditions that require system shutdown. A few examples
of these conditions are hi
This patch adds support for FSP (Flexible Service Processor)
EPOW (Early Power Off Warning) and DPO (Delayed Power Off) events for
the PowerNV platform. EPOW events are generated by FSP due to various
critical system conditions that require system shutdown. A few examples
of these conditions are hi
Why are your patches all as replies?
On Wed, 3 Jun 2015 15:08:29 +0200
Torsten Duwe wrote:
> Implement ftrace on ppc64
What do you mean "Implement ftrace on ppc64"? It's already implemented.
I'm not even going to bother looking at this patch because I have no
idea what its purpose is.
-- Ste
Hi,
I see the following lockdep splat on my RackMac machine on boot:
[6.002593] Registering G5 CPU frequency driver
[6.011288] Frequency method: i2c/pfunc, Voltage method: i2c/pfunc
[6.023605] Low: 1800 Mhz, High: 2300 Mhz, Cur: 1800 MHz
[6.038022] ===
On Mon, Jun 08, 2015 at 11:30:32AM -0400, Steven Rostedt wrote:
>
> Why are your patches all as replies?
Because I cared too much about the threading and the series that the
"Re:" escaped me.
> > Implement ftrace on ppc64
>
> What do you mean "Implement ftrace on ppc64"? It's already implemente
On 08-06-15, 18:45, Denis Kirjanov wrote:
> Hi,
>
> I see the following lockdep splat on my RackMac machine on boot:
What kernel version is it ?
--
viresh
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/li
On 6/8/15, Viresh Kumar wrote:
> On 08-06-15, 18:45, Denis Kirjanov wrote:
>> Hi,
>>
>> I see the following lockdep splat on my RackMac machine on boot:
>
> What kernel version is it ?
[6.091149] 4.1.0-rc6-01265-g908e80d-dirty #15 Not tainted
> --
> viresh
>
___
On 08-06-15, 19:37, Denis Kirjanov wrote:
> [6.091149] 4.1.0-rc6-01265-g908e80d-dirty #15 Not tainted
Sorry, this points to a dirty tree. Can you please explain what's more
than rc6 is here ? Are you using any other patches from somewhere?
--
viresh
_
Anshuman Khandual wrote on 19.05.2015
17:07:56:
>This patch series adds twelve new ELF core note sections which can
> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for
accessing
> various transactional memory and other miscellaneous debug register sets
on
> powerpc platform.
On 6/8/15, Viresh Kumar wrote:
> On 08-06-15, 19:37, Denis Kirjanov wrote:
>> [6.091149] 4.1.0-rc6-01265-g908e80d-dirty #15 Not tainted
>
> Sorry, this points to a dirty tree. Can you please explain what's more
> than rc6 is here ? Are you using any other patches from somewhere?
Ah, forgot to
On Mon, 2015-06-08 at 05:12 -0500, Lu Yangbo-B47093 wrote:
> Thanks a lot, Scott.
> And now a patch was merged on
> git://git.linaro.org/people/ulf.hansson/mmc.git next branch to fix
> this issue.
> It should be no problem.
Assuming that patch fixes it and gets pulled for 4.2, this config
patch
On Mon, 2015-06-08 at 18:06 +0800, yuantian.t...@freescale.com wrote:
> +
> +_GLOBAL(flush_caches_e500v2)
> + mflr r0
> + bl flush_dcache_L1
> + mtlr r0
> + blr
> +
> +_GLOBAL(flush_caches_e500mc)
> +_GLOBAL(flush_caches_e5500)
> + mflr r0
> + bl flush_dcache_L1
>
On Sun, 2015-06-07 at 08:54 +0100, Grant Likely wrote:
> > IE. conceptually, what overlays do today is quite rooted around the idea
> > of having a fixed "base" DT and some pre-compiled DTB overlays that
> > get added/removed. The design completely ignore the idea of a FW that
> > maintains a "live
On Mon, 2015-06-08 at 18:45 +0300, Denis Kirjanov wrote:
> Hi,
>
> I see the following lockdep splat on my RackMac machine on boot:
I don't completely understand what lockdep is trying to tell us here...
I don't "see" the deadlock.
Ben.
> [6.002593] Registering G5 CPU frequency driver
> [
Hi,
If there is anything wrong, please report it in this thread:
https://marc.info/?t=14333295573
The meaning of entries in the tables is:
| ok | # feature supported by the architecture
|TODO| # feature not yet supported by the architecture
| .. | # feature cannot be supporte
On Mon, Jun 8, 2015 at 9:57 PM, Benjamin Herrenschmidt
wrote:
> On Sun, 2015-06-07 at 08:54 +0100, Grant Likely wrote:
>> > IE. conceptually, what overlays do today is quite rooted around the idea
>> > of having a fixed "base" DT and some pre-compiled DTB overlays that
>> > get added/removed. The
From: Tang Yuantian
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback functi
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, May 27, 2015 3:38 AM
> To: Jia Hongtao-B38951
> Cc: edubez...@gmail.com; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org; robh...@kernel.org; rui.zh...@intel.com
> Subject: Re: [PATCH V2] QorIQ/TMU: add TMU node
On Fri, Jun 05, 2015 at 04:35:09PM +1000, Alexey Kardashevskiy wrote:
> So far one TCE table could only be used by one IOMMU group. However
> IODA2 hardware allows programming the same TCE table address to
> multiple PE allowing sharing tables.
>
> This replaces a single pointer to a group in a io
On Fri, Jun 05, 2015 at 04:35:19PM +1000, Alexey Kardashevskiy wrote:
> TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
> on huge guests (hundreds of GB of RAM) so the kernel might be unable to
> allocate contiguous chunk of physical memory to store the TCE table.
>
> To add
On Fri, Jun 05, 2015 at 04:35:24PM +1000, Alexey Kardashevskiy wrote:
> We are adding support for DMA memory pre-registration to be used in
> conjunction with VFIO. The idea is that the userspace which is going to
> run a guest may want to pre-register a user space memory region so
> it all gets pi
On Fri, Jun 05, 2015 at 04:35:25PM +1000, Alexey Kardashevskiy wrote:
> The existing implementation accounts the whole DMA window in
> the locked_vm counter. This is going to be worse with multiple
> containers and huge DMA windows. Also, real-time accounting would requite
> additional tracking of
On Fri, Jun 05, 2015 at 04:35:01PM +1000, Alexey Kardashevskiy wrote:
> There moves locked pages accounting to helpers.
> Later they will be reused for Dynamic DMA windows (DDW).
>
> This reworks debug messages to show the current value and the limit.
>
> This stores the locked pages number in th
On Fri, Jun 05, 2015 at 04:35:18PM +1000, Alexey Kardashevskiy wrote:
> This is a part of moving DMA window programming to an iommu_ops
> callback. pnv_pci_ioda2_set_window() takes an iommu_table_group as
> a first parameter (not pnv_ioda_pe) as it is going to be used as
> a callback for VFIO DDW c
On 06/08/2015 05:08 PM, Anshuman Khandual wrote:
> From: "khand...@linux.vnet.ibm.com"
This should be "Anshuman Khandual " and it happened
to couple of other patches in this series as well. I believe it got messed up in
a test machine, will fix it next time around.
__
On Fri, Jun 05, 2015 at 02:44:32PM -0500, Bjorn Helgaas wrote:
>On Thu, Jun 04, 2015 at 04:41:30PM +1000, Gavin Shan wrote:
>> Currently, PowerPC PowerNV platform utilizes ppc_md.pcibios_fixup(),
>> which is called for once after PCI probing and resource assignment
>> are completed, to allocate pla
This fixes compile error introduced in
"[PATCH kernel v12 17/34]
powerpc/spapr: vfio: Switch from iommu_table to new iommu_table_group".
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/pseries/iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/ps
On Fri, Jun 05, 2015 at 03:11:10PM -0500, Bjorn Helgaas wrote:
>On Thu, Jun 04, 2015 at 04:42:11PM +1000, Gavin Shan wrote:
>> The patch intends to add standalone driver to support PCI hotplug
>> for PowerPC PowerNV platform, which runs on top of skiboot firmware.
>> The firmware identified hotplug
On Sat, Jun 06, 2015 at 06:18:15AM +1000, Benjamin Herrenschmidt wrote:
>On Fri, 2015-06-05 at 15:11 -0500, Bjorn Helgaas wrote:
>
>> You didn't add this, but "pcibios_add_pci_devices" doesn't seem like the
>> right name. "pcibios" generally refers to an arch-specific hook that's
>> called by the
On Fri, Jun 05, 2015 at 02:47:30PM -0500, Bjorn Helgaas wrote:
>"Move pcibios_find_pci_bus() from pSeries to generic powerpc code"?
>
>On Thu, Jun 04, 2015 at 04:42:00PM +1000, Gavin Shan wrote:
>> The patch moves pcibios_find_pci_bus() to PPC kerenl directory so
>
>s/kerenl/kernel/
>
Thanks. I'll
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