On Wednesday 07 January 2015 03:07 PM, Alexey Kardashevskiy wrote:
> Hi!
>
> "ppc64_cpu --smt=off" produces multiple error on the latest upstream kernel
> (sha1 bdec419):
>
> NMI watchdog: BUG: soft lockup - CPU#20 stuck for 23s! [swapper/20:0]
>
> or
>
> INFO: rcu_sched detected stalls on CP
LPCR_PECE1 bit controls whether decrementer interrupts are allowed to
cause exit from power-saving mode. While waking up from winkle, restoring
LPCR with LPCR_PECE1 set (i.e Decrementer interrupts allowed) can cause
issue in the following scenario:
- All the threads in a core are offlined. The cor
of_find_node_by_name() calls of_node_put() on its "from" parameter,
which must not be done on "master", as it's still in use, and will be
released manually later. This may cause a zero kref refcount.
Use of_get_child_by_name() instead to fix this.
Signed-off-by: Geert Uytterhoeven
Cc: linuxppc-d
From: Paul Mackerras
This patch has been added to the 3.12 stable tree. If you have any
objections, please let us know.
===
commit 8117ac6a6c2fa0f847ff6a21a1f32c8d2c8501d0 upstream.
Currently, when going idle, we set the flag indicating that we are in
nap mode (paca->kvm_hstate.hwt
On 01/13/2015 07:15 PM, Michael Ellerman wrote:
> On Tue, 2015-01-13 at 17:16 -0700, Shuah Khan wrote:
>> Please add a commit log.
>
> What does it need to say?
Explain the change the patch is making. Please see
Documentation/SubmittingPatches for details.
Looks like this patch is no longer nee
On Wed, 2015-01-14 at 11:57 +, Bogdan Purcareata wrote:
> The readback is necessary in order to handle PCI posted
> writes,
That is unclear.
> or when the MPIC is handling interrupts in a loop
> (ppc_md.get_irq).
I'm questioning this one as well -- if reading WHOAMI is sufficient to
sync wi
On 01/12/2015 06:31 PM, Tyrel Datwyler wrote:
> Change maintainer of ibmvscsi driver to Tyrel Datwyler.
>
> Signed-off-by: Tyrel Datwyler
> Cc: Nathan Fontenot
> Cc: Brian King
Acked-by: Nathan Fontenot
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --
The readback is necessary in order to handle PCI posted
writes, or when the MPIC is handling interrupts in a loop
(ppc_md.get_irq). Newer MPIC versions don't require this
readback. Leave the option configurable using a device
tree entry.
This saves a MMIO trap per interrupt.
Signed-off-by: Scott
On 01/14/2015 10:01 AM, Michael Ellerman wrote:
On Wed, 2014-12-24 at 17:28 +0530, Hari Bathini wrote:
With minor checks, we can move most of the code for nvram
under pseries to a common place to be re-used by other
powerpc platforms like powernv. This patch moves such
common code to arch/powerp
Perfect. I'm glad there's a patch.
mh
On Mon, Jan 12, 2015 at 4:31 PM, Scott Wood wrote:
> On Mon, 2015-01-12 at 10:27 -0500, Martin Hicks wrote:
> >
> > With an earlier change (746c9e9f - Fix PowerPC address parsing hack),
> ethernet
> > has broken on Freescale boards such as the P1022. All r
This was a sort of unfortunate revelation on how things ‘change’.
While as it is, I found this problem, and ‘fixed’ my device tree source, had
this been for units ‘fielded’, I have to sleuth through some amount of kernel
code to find where the OF tree was parsed, and then ‘fix’ the kernel, as
ch
On Wed, 2015-01-14 at 23:35 +0530, Hari Bathini wrote:
> On 01/14/2015 10:01 AM, Michael Ellerman wrote:
>
> > On Wed, 2014-12-24 at 17:28 +0530, Hari Bathini wrote:
> > > With minor checks, we can move most of the code for nvram
> > > under pseries to a common place to be re-used by other
> > > p
Once upon a time, at least 9 years ago (< 2.6.12), _TIF_SYSCALL_T_OR_A
meant "TRACE or AUDIT". But these days it means TRACE or AUDIT or
SECCOMP or TRACEPOINT or NOHZ.
All of those are implemented via syscall_dotrace() so rename the flag to
that to try and clarify things.
Signed-off-by: Michael E
On Wed, 2015-01-14 at 16:43 +0530, Shreyas B. Prabhu wrote:
> LPCR_PECE1 bit controls whether decrementer interrupts are allowed to
> cause exit from power-saving mode. While waking up from winkle, restoring
> LPCR with LPCR_PECE1 set (i.e Decrementer interrupts allowed) can cause
> issue in the fo
We removed the last usage of CPU_FTR_IABR in commit 1ad7d70562ee
"powerpc/xmon: Enable HW instruction breakpoint on POWER8".
Mark it as free.
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/cputable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/
This patchset enables the SRIOV on POWER8.
The gerneral idea is put each VF into one individual PE and allocate required
resources like MMIO/DMA/MSI. The major difficulty comes from the MMIO
allocation and adjustment for PF's IOV BAR.
On P8, we use M64BT to cover a PF's IOV BAR, which could make
When implementing the SR-IOV on PowerNV platform, some resource reservation
is needed for VFs which don't exist at the bootup stage. To do the match
between resources and VFs, the code need to get the VF's BDF in advance.
In this patch, it exports the interface to retrieve VF's BDF:
* Make the
VFs are dynamically created/released when driver enable them. On some
platforms, like PowerNV, special resources are necessary to enable VFs.
This patch adds two hooks for platform initialization before creating the
VFs.
Signed-off-by: Wei Yang
---
drivers/pci/iov.c | 19 +++
The alignment of PF's IOV BAR is designed to be the individual size of a
VF's BAR size. This works fine for many platforms, but on PowerNV platform
it needs some change.
The original alignment works, since at sizing and assigning stage the
requirement is from an individual VF's BAR size instead of
Currently we don't store the VF BAR size, and each time we calculate the
size by dividing the PF's IOV BAR size by total_VFs.
This patch stores the VF BAR size in pci_sriov and introduces a function to
retrieve it. Also, it adds a log message to show the total PF's IOV BAR
size.
Signed-off-by: We
At resource sizing/assigning stage, resources are divided into two lists,
requested list and additional list, while the alignement of the additional
IOV BAR is not taken into the sizing and assigning procedure.
This is reasonable in the original implementation, since IOV BAR's
alignment is mostly
In order to enable SRIOV on PowerNV platform, the PF's IOV BAR needs to be
adjusted:
1. size expaned
2. aligned to M64BT size
This patch documents this change on the reason and how.
Signed-off-by: Wei Yang
---
.../powerpc/pci_iov_resource_on_powernv.txt| 215 +++
If we're going to reassign resources with flag PCI_REASSIGN_ALL_RSRC, all
resources will be cleaned out during device header fixup time and then get
reassigned by PCI core. However, the VF resources won't be reassigned and
thus, we shouldn't clean them out.
This patch adds a condition. If the pci_
From: Gavin Shan
pci_dn is the extension of PCI device node and it's created from
device node. Unfortunately, VFs that are enabled dynamically by
PF's driver and they don't have corresponding device nodes, and
pci_dn. The patch refactors pci_dn to support VFs:
* pci_dn is organized as a hiera
The field pci_dn->pcidev is assigned but not used.
This patch removes this field.
Signed-off-by: Wei Yang
Acked-by: Gavin Shan
---
arch/powerpc/include/asm/pci-bridge.h |1 -
arch/powerpc/platforms/powernv/pci-ioda.c |1 -
2 files changed, 2 deletions(-)
diff --git a/arch/powerpc/
The PCI config accessors rely on device node. Unfortunately, VFs
don't have corresponding device nodes. So we have to switch to
pci_dn for PCI config access.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 14 +-
arch/powerpc/platforms/powernv/pci.c |
Current iommu_table of a PE is a static field. This will have a problem
when iommu_free_table is called.
This patch allocate iommu_table dynamically.
Signed-off-by: Wei Yang
---
arch/powerpc/include/asm/iommu.h |3 +++
arch/powerpc/platforms/powernv/pci-ioda.c | 26 ++
On PHB3, PF IOV BAR will be covered by M64 BAR to have better PE isolation.
Mostly the total_pe number is different from the total_VFs, which will lead
to a conflict between MMIO space and the PE number.
For example, total_VFs is 128 and total_pe is 256, then the second half of
M64 BAR space will
This patch implements the pcibios_iov_resource_alignment() on powernv
platform.
On PowerNV platform, there are 3 cases for the IOV BAR:
1. initial state, the IOV BAR size is multiple times of VF BAR size
2. after expanded, the IOV BAR size is expanded to meet the M64 segment size
3. sizing stage,
VFs are created, when pci device is enabled.
This patch tries best to assign maximum resources and PEs for VF when pci
device is enabled. Enough M64 assigned to cover the IOV BAR, IOV BAR is
shifted to meet the PE# indicated by M64. VF's pdn->pdev and
pdn->pe_number are fixed.
Signed-off-by: Wei
On PowrNV platform, resource position in M64 implies the PE# the resource
belongs to. In some particular case, adjustment of a resource is necessary
to locate it to a correct position in M64.
This patch introduces a function to shift the 'real' PF IOV BAR address
according to an offset.
Signed-of
M64 aperture size is limited on PHB3. When the IOV BAR is too big, this
will exceed the limitation and failed to be assigned.
This patch introduce a different mechanism based on the IOV BAR size:
IOV BAR size is smaller than 64M, expand to total_pe.
IOV BAR size is bigger than 64M, roundup power2
When IOV BAR is big, each of it is covered by 4 M64 window. This leads to
several VF PE sits in one PE in terms of M64.
This patch group VF PEs according to the M64 allocation.
Signed-off-by: Wei Yang
---
arch/powerpc/include/asm/pci-bridge.h |2 +-
arch/powerpc/platforms/powernv/pci-io
PING!
Thanks,
Yuantian
> -Original Message-
> From: Kevin Hao [mailto:haoke...@gmail.com]
> Sent: Wednesday, December 03, 2014 4:54 PM
> To: linuxppc-dev@lists.ozlabs.org
> Cc: Benjamin Herrenschmidt; Wood Scott-B07421; Mike Turquette; Lu
> Jingchang-B35083; Gerhard Sittig; Tang Yuantian-
Add mode to opal call. SNOOP control turns CAPP unit snooping on/off. This is
needed for the following reset patch, which turns snoops off in the CAPP
recovery path.
Signed-off-by: Ryan Grimm
---
arch/powerpc/include/asm/opal.h | 12
arch/powerpc/include/asm/pnv-pci.h
Add reset_loads_image and reset_image_select to sysfs.
reset_image_select identifies which image will be loaded to the card on the
next PERST. Valid entries are: "user" and "factory".
reset_loads_image defines functionality on a PERST. Value of 0 means PERST
will not cause image load. A power
This allows an image to be downloaded to the flash without rebooting the
machine. The driver perform a PERST, which results in FPGA image downloaded to
flash and the CAPP unit enters recovery. CAPP recovery triggers an HMI, which
is handled by EEH in Linux. EEH removes the driver, calls into Sap
On Mon, 2014-11-24 at 15:07 +0100, Laurent Dufour wrote:
> On pseries system (LPAR) xmon failed to enter when running in LE mode, system
> is hunging. Inititating xmon will lead to such an output on the console:
>
> SysRq : Entering xmon
> cpu 0x15: Vector: 0 at [c003f39ffb10]
> pc: c
Some bios put range that is not fully coverred by root bus resources.
Try to clip them and update them in pci bridge bars.
We'd like to fix other arches instead of just x86.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491
Reported-by: Marek Kordik
Fixes: 5b28541552ef ("PCI: Restrict 64-b
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:39 +1100:
> Add reset_loads_image and reset_image_select to sysfs.
>
> reset_image_select identifies which image will be loaded to the card on the
> next PERST. Valid entries are: "user" and "factory".
>
> reset_loads_image defines functiona
Excerpts from Ian Munsie's message of 2015-01-15 15:41:24 +1100:
> At the moment we don't set it at boot - we just go with whatever the
> card is already set to do. I'm thinking it might be a good idea to
> always set this bit on boot so the only time it's disabled is if a user
> has explicitly gon
> While I think of it - if we change this on boot we should also change
> reset_image_select to match the currently loaded image. e.g. if
> reset_loads_image has defaulted to off and reset_image_select has
> defaulted to factory, but the user image has been loaded - that way we
> avoid unexpectedly
On Thu, 2015-01-15 at 15:41 +1100, Ian Munsie wrote:
> Excerpts from Ryan Grimm's message of 2015-01-15 13:56:39 +1100:
> > Add reset_loads_image and reset_image_select to sysfs.
> >
> > reset_image_select identifies which image will be loaded to the card on the
> > next PERST. Valid entries are:
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:40 +1100:
> Add mode to opal call. SNOOP control turns CAPP unit snooping on/off. This
> is
> needed for the following reset patch, which turns snoops off in the CAPP
> recovery path.
Looking at patch 3 in this series I think this descripti
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:41 +1100:
> This allows an image to be downloaded to the flash without rebooting the
> machine. The driver perform a PERST, which results in FPGA image downloaded
> to
> flash and the CAPP unit enters recovery. CAPP recovery triggers an HMI,
Excerpts from Michael Ellerman's message of 2015-01-15 16:07:17 +1100:
> > Of the two names I'd probably go with reset_image_select.
>
> Three words, all can be verbs, two can be nouns, it's not too clear.
>
> Maybe "load_image_on_perst" ?
Works for me :)
Cheers,
-Ian
_
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:41 +1100:
> +What: /sys/class/cxl//reset
> +Date: October 2014
> +Contact:linuxppc-dev@lists.ozlabs.org
> +Description:write only
> +Writing 1 here will issue a PERST to card.
...
> +static ssiz
From: Tang Yuantian
Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untou
From: Tang Yuantian
redefine variable clocks_per_pll as a struct member
If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.
Signed-off-by: Tang Yuantian
---
These patches are based on following three patches which are acke
From: Wang Dongsheng
U-boot put non-boot cpus into an low power state(PW10/PW20 or DOZE) when cpu
powered up. To exit low power state kernel will send DOORBELL or MPIC-IPI
signal to all those CPUs.
e500/e500v2 use mpic to send IPI signal.
e500mc and later use doorbell to send IPI signal.
This f
> > @@ -806,8 +837,8 @@ static int cxl_read_vsec(struct cxl *adapter, struct
> > pci_dev *dev)
> > CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
> > CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
> > adapter->user_image_loaded = !!(image_state &
> > CXL_VSEC_USER_
Hi Linus,
Please pull some more powerpc fixes for 3.19:
The following changes since commit eaa27f34e91a14cdceed26ed6c6793ec1d186115:
linux 3.19-rc4 (2015-01-11 12:44:53 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux.git
tags/powerpc-
Hi all,
U-boot patch link:
http://patchwork.ozlabs.org/patch/429265/
Regards,
-Dongsheng
> -Original Message-
> From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com]
> Sent: Thursday, January 15, 2015 2:06 PM
> To: Wood Scott-B07421; Sun York-R58495; Li Yang-Leo-R58472
> Cc: linuxpp
53 matches
Mail list logo
