On Mon, 2014-06-02 at 11:20 +1000, Michael Ellerman wrote:
> __attribute__ ((unused))
>
> WSP is the last user of CONFIG_PPC_A2, so we remove that as well.
>
> Although CONFIG_PPC_ICSWX still exists, it's no longer selectable for
> any Book3E platform, so we can remove the code in mmu-book3e.h th
On 06/01/2014 11:48 AM, Michael Neuling wrote:
> On Fri, 2014-05-30 at 17:40 +0530, Anshuman Khandual wrote:
>> This patch enables support for hardware instruction breakpoints on POWER8
>> with
>> the help of a new register called CIABR (Completed Instruction Address
>> Breakpoint
>> Register). W
On Wednesday 21 May 2014 12:02 PM, Sam Bobroff wrote:
> Split the __SYSFS_SPRSETUP macro into two parts so that registers requiring
> custom read and write functions can use common code for their show and store
> functions.
>
> Signed-off-by: Sam Bobroff
> ---
> arch/powerpc/kernel/sysfs.c | 1
On Wednesday 21 May 2014 12:02 PM, Sam Bobroff wrote:
> Since commit "efcac65 powerpc: Per process DSCR + some fixes (try#4)"
> it is no longer possible to set the DSCR on a per-CPU basis.
>
> The old behaviour was to minipulate the DSCR SPR directly but this is no
> longer sufficient: the value i
On 05/31/2014 01:45 AM, Scott Wood wrote:
From: Laurentiu Tudor
Virtualized environments may expose a e6500 dual-threaded core
as two single-threaded e6500 cores. Take advantage of this
and get rid of the tlb lock and the trap-causing tlbsx in
the htw miss handler by guarding with CPU_FTR_SMT,
On Wed, May 28, 2014 at 10:04 AM, Anshuman Khandual
wrote:
> On 05/27/2014 05:39 PM, Stephane Eranian wrote:
>> I have been looking at those patches and ran some tests.
>> And I found a few issues so far.
>>
>> I am running:
>> $ perf record -j any_ret -e cycles:u test_program
>> $ perf report -D
The commit 1d628af7 "add load inst fixup" made an attempt to handle
failures generated by reading the guest current instruction. The fixup
code that was added works by chance hiding the real issue.
Load external pid (lwepx) instruction, used by KVM to read guest
instructions, is executed in a subs
Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E.
Signed-off-by: Mihai Caraman
---
v3:
- no change
v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an infinite loop caused by lwepx's data TLB miss
e
On book3e, KVM uses load external pid (lwepx) dedicated instruction to read
guest last instruction on the exit path. lwepx exceptions (DTLB_MISS, DSI
and LRAT), generated by loading a guest address, needs to be handled by KVM.
These exceptions are generated in a substituted guest translation contex
On book3e, guest last instruction is read on the exit path using load
external pid (lwepx) dedicated instruction. This load operation may fail
due to TLB eviction and execute-but-not-read entries.
This patch lay down the path for an alternative solution to read the guest
last instruction, by allow
eshe...@gmail.com wrote:
I have another question. Did you test full duplex in P1022 RDK board?
Our design is same with P1022 RDK.
No, I don't think I did. The P1022RDK was not a board that my team was
responsible for, so I only did minimal work on it. I added support for
it in the upstream
On 06/02/2014 06:29 PM, Stephane Eranian wrote:
> On Wed, May 28, 2014 at 10:04 AM, Anshuman Khandual
> wrote:
>> On 05/27/2014 05:39 PM, Stephane Eranian wrote:
>>> I have been looking at those patches and ran some tests.
>>> And I found a few issues so far.
>>>
>>> I am running:
>>> $ perf recor
On Mon, Jun 2, 2014 at 6:04 PM, Anshuman Khandual
wrote:
> On 06/02/2014 06:29 PM, Stephane Eranian wrote:
>> On Wed, May 28, 2014 at 10:04 AM, Anshuman Khandual
>> wrote:
>>> On 05/27/2014 05:39 PM, Stephane Eranian wrote:
I have been looking at those patches and ran some tests.
And I
On Mon, 2014-06-02 at 15:48 +0300, Tudor Laurentiu wrote:
> On 05/31/2014 01:45 AM, Scott Wood wrote:
> > From: Laurentiu Tudor
> > - resent since the original didn't make it to the list archives
> > or patchwork.
>
> The only thing i can think of is that maybe i've misspelled the mailing
Hi Timur
thanks for your repons.
I have another question. Did you test full duplex in P1022 RDK board?Our design
is same with P1022 RDK.
B.R.杨小帅
From: Timur TabiDate: 2014-05-30 23:48To: eshe168CC: linuxppc-dev;
zhphsearchSubject: Re: P1022 audio driver help!On 05/30/2014 01:03 AM, eshe168
Hi,
> This patch enables POWER8 doorbell IPIs on powernv.
>
> Since doorbells can only IPI within a core, we test to see when we
> can use doorbells and if not we fall back to XICS. This also enables
> hypervisor doorbells to wakeup us up from nap/sleep via the LPCR
> PECEDH bit.
>
> Based on t
On Mon, 2014-06-02 at 14:59 +0200, Stephane Eranian wrote:
> On Wed, May 28, 2014 at 10:04 AM, Anshuman Khandual
> wrote:
> > On 05/27/2014 05:39 PM, Stephane Eranian wrote:
> >> I have been looking at those patches and ran some tests.
> >> And I found a few issues so far.
> >>
> >> I am running:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the kvm on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
From my guess, it is caused by some needs on bitmap management. Kvm side
wants to maintain bitma
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the kvm on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
From my guess, it is caused by some needs on bitmap management. Kvm side
wants to maintain bitma
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
Signed-off-by: Joonsoo Kim
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index b3fe1cc..4eac559 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
Now, we have general CMA reserved area management framework,
so use it for future maintainabilty. There is no functional change.
Signed-off-by: Joonsoo Kim
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c
b/arch/powerpc/kvm/book3s_hv_builtin.c
index 8cd0dae..43c3f81 100644
--- a/arch/powerpc/k
On Tue, May 20, 2014 at 01:25:11PM +0200, Alexander Graf wrote:
>
> On 20.05.14 10:30, Gavin Shan wrote:
> >If we detects frozen state on PE that has been passed to guest, we
> >needn't handle it. Instead, we rely on the guest to detect and recover
> >it. The patch avoid EEH event on the frozen pa
On 05/30/2014 07:12 PM, Aneesh Kumar K.V wrote:
> Anshuman Khandual writes:
>
>> This patch enables support for hardware instruction breakpoints on POWER8
>> with
>> the help of a new register called CIABR (Completed Instruction Address
>> Breakpoint
>> Register). With this patch, single hardwa
On Tue, Jun 03 2014, Joonsoo Kim wrote:
> Currently, there are two users on CMA functionality, one is the DMA
> subsystem and the other is the kvm on powerpc. They have their own code
> to manage CMA reserved area even if they looks really similar.
> From my guess, it is caused by some needs on bit
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