On Fri, Aug 09, 2013 at 04:25:04PM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2013-08-07 at 18:15 -0500, Fionnuala Gunter wrote:
> > This patch fixes a bug that is triggered when cts(cbc(aes)) is used with
> > nx-crypto driver on input larger than 32 bytes.
> >
> > The chaining value from co-p
On Tue, 2013-08-06 at 15:44 -0500, Nathan Fontenot wrote:
> I am planning on pulling the first two patches and sending them out
> separate from the patch set since they are really independent of the
> rest of the patch series.
>
> The remaining code I will send out for review and inclusion in
> li
On 07/04/2013 08:35 AM, Paul Mackerras wrote:
Some systems have an ibm,chip-id property in the cpu nodes in the
device tree. On these systems, we now use that to compute the
cpu_core_mask (i.e. the set of core siblings) rather than looking
at cache properties.
Paul,
I wanted to test this pat
This reworks the Facility Status and Control Regsiter (FSCR) config bit
definitions so that we can access the bit numbers. This is needed for a
subsequent patch to fix the userspace DSCR handling.
HFSCR and FSCR bit definitions are the same, so reuse them.
Signed-off-by: Michael Neuling
Cc: [v
Currently if we take hypervisor facility unavaliable (from 0xf80/0x4f80) we
mark it as an OS facility unavaliable (0xf60) as the two share the same code
path.
The becomes a problem in facility_unavailable_exception() as we aren't able to
see the hypervisor facility unavailable exceptions.
Below f
POWER8 allows the DSCR to be accessed directly from userspace via a new SPR
number 0x3 (Rather than 0x11. DSCR SPR number 0x11 is still used on POWER8 but
like POWER7, is only accessible in HV and OS modes). Currently, we allow this
by setting H/FSCR DSCR bit on boot.
Unfortunately this doesn't
This moves us to save the Target Address Register (TAR) a earlier in
__switch_to. It introduces a new function save_tar() to do this.
We need to save the TAR earlier as we will overwrite it in the transactional
memory reclaim/recheckpoint path. We are going to do this in a subsequent
patch which
If a transaction is rolled back, the Target Address Register (TAR), Processor
Priority Register (PPR) and Data Stream Control Register (DSCR) should be
restored to the checkpointed values before the transaction began. Any changes
to these SPRs inside the transaction should not be visible in the ab
On Wed, 2013-08-07 at 02:01 -0400, Mike Qiu wrote:
> 'pe_no' hasn't been defined, it should be an typo error,
> it should be 'frozen_pe_no'.
For some reason I can't find v3 of this in my mailbox, but it's
on patchwork so I tried applying it and it breaks the build
because %d doesn't work for a u64
Hi Linus !
Here are some powerpc fixes for you.
This includes small series from Michael Neuling to fix a couple of nasty
remaining problems with the new Power8 support, also targeted at stable
3.10, without which some new userspace accessible registers aren't
properly context switched, and in som
On Thursday 08 August 2013 09:38 AM, Aruna Balakrishnaiah wrote:
Hi Tony,
On Thursday 08 August 2013 03:52 AM, Tony Luck wrote:
On Tue, Aug 6, 2013 at 10:35 PM, Tony Luck wrote:
ERST is at the whim of the BIOS writer (the ACPI standard doesn't provide any
suggestions on record sizes). My sys
On Aug 9, 2013, at 1:24 AM, Stephen Rothwell wrote:
> We cannot put the unsetting of config options in the Kconfig file, nor
> the integer or string options.
>
> I checked that after this we get the same .config files generated (except
> for the addition of the new PPC64_DEFCONFIG* config option
On Aug 9, 2013, at 1:03 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-08-08 at 17:45 -0500, Scott Wood wrote:
>> The following changes since commit 3b2f64d00c46e1e4e9bd0bb9bb12619adac27a4b:
>>
>> Linux 3.11-rc2 (2013-07-21 12:05:29 -0700)
>>
>> are available in the git repository at:
>
> N
On Jul 31, 2013, at 1:25 AM, Haijun Zhang wrote:
> Add function to support get voltage from device-tree.
> If there are voltage-range specified in device-tree node, this function
> will parse it and return the avail voltage mask.
>
> Signed-off-by: Haijun Zhang
> ---
> changes for v2:
> -
Memory hotplug on Power is currently broken, these two patches correct the
issues needed to get memory hotplug working again.
This update marks memory resources that are added at boot time are also
marked as busy. It sounds a bit counter intuitive but the core mm code will
not free memory resource
Memory resources should be marked as busy.
If memory resources are not marked as busy they do not get released during
hotplug memory remove. This seems a bit counter intuitive but the core
kernel resource code checks for the IORESOURCE_BUSY flag before releasing
the resource.
Signed-off-by: Natha
Register bootmem pages at boot time on powerpc.
Previous commit 46723bfa540... introduced a new config option,
HAVE_BOOTMEM_INFO_NODE, to enable registering of bootmem pages. As a result
the bootmem pages for powerpc are not registered since we do not define this.
This causes a BUG_ON in put_page_
On Fri, 2013-08-09 at 09:43 -0500, Kumar Gala wrote:
> On Aug 9, 2013, at 1:03 AM, Benjamin Herrenschmidt wrote:
>
> > On Thu, 2013-08-08 at 17:45 -0500, Scott Wood wrote:
> >> The following changes since commit
> >> 3b2f64d00c46e1e4e9bd0bb9bb12619adac27a4b:
> >>
> >> Linux 3.11-rc2 (2013-07-21
I am tryng to compile clean mainline kernel with a few different config files
and running into errors with some configs.
I am building on RHEL6.3 with following binaries:
gcc (GCC) 4.4.6 20120305 (Red Hat 4.4.6-4)
GNU ld version 2.20.51.0.2-5.34.el6 20100205
binutils-2.20
Until now, the MSI architecture-specific functions could be overloaded
using a fairly complex set of #define and compile-time
conditionals. In order to prepare for the introduction of the msi_chip
infrastructure, it is desirable to switch all those functions to use
the 'weak' mechanism. This commit
Now that we have weak versions for each of the PCI MSI architecture
functions, we can actually build the MSI support for all platforms,
regardless of whether they provide or not architecture-specific
versions of those functions. For this reason, the ARCH_SUPPORTS_MSI
hidden kconfig boolean becomes
On Aug 9, 2013, at 1:24 PM, Sukadev Bhattiprolu wrote:
>
> I am tryng to compile clean mainline kernel with a few different config files
> and running into errors with some configs.
>
> I am building on RHEL6.3 with following binaries:
>
> gcc (GCC) 4.4.6 20120305 (Red Hat 4.4.6-4)
>
On Thu, 2013-08-08 at 07:50 +0200, leroy christophe wrote:
> Le 26/06/2013 01:04, Scott Wood a écrit :
> > What happens if there's a race? If another CPU updates wdt_last_ping in
> > parallel, then you could see wdt_last_ping greater than the value you
> > read for jiffies. Since this is an unsig
Kumar Gala [ga...@kernel.crashing.org] wrote:
|
| >
| > The pre-processor output for the first WARN_ON() is:
| >
| > ---
| > ({ int __ret_warn_on = !!(nr < 0 || nr >= 32); if
(__builtin_constant_p(__ret_warn_on)) { if (__ret_warn_on) do { __asm__
__volatile__( "1:twi 31,0,0\n" ".section __
On Tue, 2013-08-06 at 17:01 +0530, Bharat Bhushan wrote:
> @@ -449,7 +446,16 @@ static inline int kvmppc_e500_shadow_map(struct
> kvmppc_vcpu_e500 *vcpu_e500,
> gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1);
> }
>
> - kvmppc_e500_ref_setup(ref, gtlbe, pfn);
> + pgdir =
This factors out the details of updating cpu_core_mask into a separate
function, to make it easier to change how the mask is calculated later.
This makes no functional change.
Signed-off-by: Paul Mackerras
---
arch/powerpc/kernel/smp.c | 56 +++
1 file
Some systems have an ibm,chip-id property in the cpu nodes in the
device tree. On these systems, we now use that to compute the
cpu_core_mask (i.e. the set of core siblings) rather than looking
at cache properties.
Signed-off-by: Paul Mackerras
---
arch/powerpc/kernel/smp.c | 47 +++
On Fri, Aug 09, 2013 at 12:52:12PM +0530, Vasant Hegde wrote:
> Paul,
>
> I wanted to test this patch but not able to apply this patch on top
> of Linux tree. Looks like I'm missing traverse_core_siblings()
> related patch. I searched in ppc mailing list and couldn't figure
> out.
Oops, my fault,
Uses of get_current() that normally get optimized away still result in
a load instruction of the current pointer in 64-bit because the inline
asm uses __volatile__. This patch removes __volatile__ so that nop-ed
uses of get_current() don't actually result in a load of the pointer.
Signed-off-by:
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