On Sun, Jun 16, 2013 at 03:12:11PM +1000, Benjamin Herrenschmidt wrote:
>On Sat, 2013-06-15 at 17:03 +0800, Gavin Shan wrote:
>> On PowerNV platform, the EEH event is produced either by detect
>> on accessing config or I/O registers, or by interrupts dedicated
>> for EEH report. The patch adds supp
On Sun, 2013-06-16 at 15:27 +0800, Gavin Shan wrote:
> Thanks for the review, Ben.
>
> >Getting better but:
> >
> > - I still don't like having a kthread for that. Why not use schedule_work()
> > ?
> >
>
> Ok. Will update it with schedule_work() in next revision :-)
>
> > - We already have
On 05.06.2013, at 08:11, Alexey Kardashevskiy wrote:
> This adds real mode handlers for the H_PUT_TCE_INDIRECT and
> H_STUFF_TCE hypercalls for QEMU emulated devices such as IBMVIO
> devices or emulated PCI. These calls allow adding multiple entries
> (up to 512) into the TCE table in one call w
On 05.06.2013, at 08:11, Alexey Kardashevskiy wrote:
> This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
> and H_STUFF_TCE requests without passing them to QEMU, which should
> save time on switching to QEMU and back.
>
> Both real and virtual modes are supported - whenever the
On Wed, 2013-06-05 at 16:11 +1000, Alexey Kardashevskiy wrote:
> +long kvm_vm_ioctl_create_spapr_tce_iommu(struct kvm *kvm,
> + struct kvm_create_spapr_tce_iommu *args)
> +{
> + struct kvmppc_spapr_tce_table *tt = NULL;
> + struct iommu_group *grp;
> + struct iommu_t
On Sun, 2013-06-16 at 14:06 +1000, Benjamin Herrenschmidt wrote:
> Look at patches http://patchwork.ozlabs.org/patch/248920/ and followup,
> he basically walks the page tables here in a slightly different way than
> Paul does in H_ENTER. It's more like gup_fast. It will need to handle
> concurrent
Hi Scott,
please see my comments.
On 06/15/2013 05:53 AM, Scott Wood wrote:
On 06/14/2013 03:39:26 PM, Scott Wood wrote:
On 06/14/2013 02:15:55 AM, Minghuan Lian wrote:
+msi0: msi@41600 {
+compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
More specific compatibles come first -- and I do
On Sun, 2013-06-16 at 16:30 +1000, Erik de Castro Lopo wrote:
> Been busy, but I'm back looking at this.
>
> David Laight wrote:
>
> > With a scratch register there are some two instruction sequences.
> > Reusing the destination register something like:
> >
> > addis %r30,%r31,hi(.label - 1
Hi Scott,
please see my comments inline.
On 06/15/2013 06:09 AM, Scott Wood wrote:
On 06/14/2013 02:15:56 AM, Minghuan Lian wrote:
@@ -421,10 +440,29 @@ static int fsl_of_msi_probe(struct
platform_device *dev)
}
msi->msiir_offset =
features->msiir_offset + (res.
On Mon, 2013-06-17 at 08:39 +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2013-06-05 at 16:11 +1000, Alexey Kardashevskiy wrote:
> > +long kvm_vm_ioctl_create_spapr_tce_iommu(struct kvm *kvm,
> > + struct kvm_create_spapr_tce_iommu *args)
> > +{
> > + struct kvmppc_spapr_tce_ta
On Sun, 2013-06-16 at 21:13 -0600, Alex Williamson wrote:
> IOMMU groups themselves don't provide security, they're accessed by
> interfaces like VFIO, which provide the security. Given a brief look, I
> agree, this looks like a possible backdoor. The typical VFIO way to
> handle this would be t
Hi Soctt,
please see my comments.
On 06/15/2013 06:06 AM, Scott Wood wrote:
On 06/14/2013 02:15:57 AM, Minghuan Lian wrote:
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses diffe
On 06/15/2013 06:10 AM, Scott Wood wrote:
On 06/14/2013 02:15:58 AM, Minghuan Lian wrote:
For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. For the
first register, when using MSIIR we will get the irqs 0x0 0x1 0x2
...0x1f, bu
Hi Scott,
please see my comments inline.
On 06/15/2013 06:13 AM, Scott Wood wrote:
On 06/14/2013 02:15:59 AM, Minghuan Lian wrote:
1. Only MSIIR1 can index 16 MSI registers, but when using MSIIR1
the IRQs of a register are not continuous. for example, the first
register irq values are 0x0, 0x1
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, June 14, 2013 12:51 AM
> To: Wang Dongsheng-B40534
> Cc: Wood Scott-B07421; b...@kernel.crashing.org;
> johan...@sipsolutions.net; an...@enomsg.org; ga...@kernel.crashing.org;
> linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PA
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