20.07.2012 18:46, Andrey Gusev пишет:
Hi!
I build kernel from git and can see errors in dmesg on boot. 3.4.5
doesn't have such issue.
git show | head -n2
commit 85efc72a0218335324d358ac479a04c16316fd4d
Actual for 3.5.0
[ 2.841441] i2c /dev entries driver
[ 2.850155] i2c i2c-0: therm_windtunne
> > For flexibility you need to allow for 8bit samples being converted
as:
> > 1) 8bit raw ulaw or alaw data (unchanged from line).
> > 2) 8bit raw data, bit reversed, any hdlc protocol
> >is bit reversed from audio [1].
> > 3) 8bit audio, converted from alaw to ulaw
> > 4) 8bit audio, converte
> > +/*
> > + * Recursively scan all the children nodes of parent and find out if
> there
> > + * is "isa" node. Return 1 if parent has isa node otherwise return 0.
> > + */
> > +int has_isa_node(struct device_node *parent)
> > +{
> > + static int result;
> > + struct device_node *cur_child;
>
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
is called at board_setup_arch stage. Now the initialization is done in
probe function which is architectural better. Also It's convenient for
adding PM
PCI initialization is called later than swiotlb_init() due to PCI controller is
a platform driver now. So we provide a function which called at board setup_arch
stage to address swiotlb enable by parsing pci ranges.
This patch depends on the following patch:
powerpc/fsl-pci: Unify pci/pcie initial
PCI host bridge is primary bus if it contains an ISA node. But not all boards
fit this rule. Device tree should be updated for all these boards.
Signed-off-by: Jia Hongtao
Signed-off-by: Li Yang
---
arch/powerpc/include/asm/pci-bridge.h |1 +
arch/powerpc/sysdev/fsl_pci.c | 31 +++
PCI initialization is now done by PCI controller driver. In board setup_arch
stage we don't need PCI init any more but swiotlb should be determined at this
stage.
Signed-off-by: Jia Hongtao
Signed-off-by: Li Yang
---
We now just apply this for mpc85xx_ds and qemu
arch/powerpc/platforms/85xx/mp
Power supply for PCI inbound/outbound window registers is off when system
go to deep-sleep state. We save the values of registers before suspend
and restore to registers after resume.
Signed-off-by: Jiang Yutang
Signed-off-by: Jia Hongtao
Signed-off-by: Li Yang
---
arch/powerpc/include/asm/pci
From: Chunhe Lan
Now we registered pci controllers as platform devices. It will make edac
driver failed to register pci nodes as platform devices too. So we combine
two initialization code as one platform driver.
Signed-off-by: Chunhe Lan
Signed-off-by: Li Yang
Signed-off-by: Jia Hongtao
---
On Wed, 2012-07-25 at 11:29 +0400, Andrey Gusev wrote:
> 20.07.2012 18:46, Andrey Gusev пишет:
> > Hi!
> > I build kernel from git and can see errors in dmesg on boot. 3.4.5
> > doesn't have such issue.
> > git show | head -n2
> > commit 85efc72a0218335324d358ac479a04c16316fd4d
Ok, so:
> Actual
> -Original Message-
> From: David Laight [mailto:david.lai...@aculab.com]
> Sent: Wednesday, July 25, 2012 2:14 PM
> To: Aggrwal Poonam-B10812; Singh Sandeep-B37400; linuxppc-
> d...@lists.ozlabs.org
> Cc: Singh Sandeep-B37400
> Subject: RE: [1/3][PATCH][upstream]Adding documentation for
25.07.2012 14:17, Benjamin Herrenschmidt пишет:
On Wed, 2012-07-25 at 11:29 +0400, Andrey Gusev wrote:
20.07.2012 18:46, Andrey Gusev пишет:
Hi!
I build kernel from git and can see errors in dmesg on boot. 3.4.5
doesn't have such issue.
git show | head -n2
commit 85efc72a0218335324d358ac479a04c
Hi,
This patchset include patches for supporting 64TB with ppc64. I haven't booted
this on hardware with 64TB memory yet. But they boot fine on real hardware with
less memory. Changes extend VSID bits to 38 bits for a 256MB segment
and 26 bits for 1TB segments.
Canges from v3:
* Address review
From: "Aneesh Kumar K.V"
ASM_VSID_SCRAMBLE can leave non-zero bits in the high 28 bits of the result
for 256MB segment (40 bits for 1T segment). Properly mask them before using
the values in slbmte
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb_low.S | 12 ++--
1 file change
From: "Aneesh Kumar K.V"
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |6 ++-
arch/powerpc/include/asm/page_64.h|6 ++-
ar
From: "Aneesh Kumar K.V"
As we keep increasing PGTABLE_RANGE we need not increase the virual
map area for kernel.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arc
From: "Aneesh Kumar K.V"
This patch convert different functions to take virtual page number
instead of virtual address. Virtual page number is virtual address
shifted right by VPN_SHIFT (12) bits. This enable us to have an
address range of upto 76 bits.
Signed-off-by: Aneesh Kumar K.V
---
arch
From: "Aneesh Kumar K.V"
Rename the variable to better reflect the values. No functional change
in this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s.h |2 +-
arch/powerpc/include/asm/machdep.h |6 +--
arch/powerpc/include/asm/mmu-hash64.h |
From: "Aneesh Kumar K.V"
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/paca.h |2 +-
arch/powerpc/mm/slb_low.S |8
2 files changed, 5 insertio
From: "Aneesh Kumar K.V"
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h| 14 +-
arch/powerpc/include/asm/pgtable-ppc64-4k.h |2 +-
arch/powerpc/include/asm/pgt
From: "Aneesh Kumar K.V"
We should do rldimi r10,r9,USER_ESID_BITS,0 only after populating
r10 with ESID bits.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb_low.S | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/power
From: "Aneesh Kumar K.V"
The proto-VSID space is divided into two class
User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
With KERNEL_START at 0xc000, the proto vsid for
the kernel ends up with 0xc (36 bits). With
From: "Aneesh Kumar K.V"
This patch simplify hpte_decode for easy switching of virtual address to
virtual page number in the later patch
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 49 ++
1 file chang
From: "Aneesh Kumar K.V"
slice array size and slice mask size depend on PGTABLE_RANGE. We
can't directly include pgtable.h in these header because there is
a circular dependency. So add compile time check for these values.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64
From: "Aneesh Kumar K.V"
Don't open code the same
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/cell/beat_htab.c
b/arch/powerpc/platforms/ce
MAX_CONTEXT change in this patch was not related. So may be we need it
to be a separate patch ?
-aneesh
>From c67fb1b973c317f114ee256110cfc1b016dc1841 Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V"
Date: Wed, 25 Jul 2012 18:34:12 +0530
Subject: [PATCH -V4] arch/powerpc: Replace open coded C
On 07/24/2012 09:35 PM, Jia Hongtao-B38951 wrote:
>
>
>> -Original Message-
>> From: Wood Scott-B07421
>> Sent: Wednesday, July 25, 2012 2:43 AM
>> To: Jia Hongtao-B38951
>> Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
>> B07421; Li Yang-R58472
>> Subject: Re:
On 07/24/2012 09:42 PM, Jia Hongtao-B38951 wrote:
>
>
>> -Original Message-
>> From: Wood Scott-B07421
>> Sent: Wednesday, July 25, 2012 2:48 AM
>> To: Jia Hongtao-B38951
>> Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
>> B07421; Li Yang-R58472
>> Subject: Re:
On 07/25/2012 04:01 AM, Jia Hongtao-B38951 wrote:
>>> +/*
>>> + * Recursively scan all the children nodes of parent and find out if
>> there
>>> + * is "isa" node. Return 1 if parent has isa node otherwise return 0.
>>> + */
>>> +int has_isa_node(struct device_node *parent)
>>> +{
>>> + static in
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit I
On Jul 25, 2012, at 1:17 PM, Timur Tabi wrote:
> Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
> is similar to the P5020DS. Features of the P5040 are listed below, but
> not all of these features (e.g. DPAA networking) are currently supported.
>
> Four P5040 single
The PCI controller on the Freescale P5040 is v2.4.
Signed-off-by: Timur Tabi
---
arch/powerpc/sysdev/fsl_pci.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a7b2a60..50a38b3 100644
--- a/arch/powerpc/s
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit I
Add device tree (dtsi) files for the Freescale P5040 SOC. Since this
SOC introduces SEC v5.2, add the dtsi file for that also.
Signed-off-by: Timur Tabi
---
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 320 +
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi| 111 +
On Wed, 25 Jul 2012 16:59:49 -0500
Timur Tabi wrote:
> Add device tree (dtsi) files for the Freescale P5040 SOC. Since this
> SOC introduces SEC v5.2, add the dtsi file for that also.
>
> Signed-off-by: Timur Tabi
> ---
mind retaining the original authors' signoffs?
Kim
On Jul 25, 2012, at 5:38 PM, "Phillips Kim-R1AAHA" wrote:
> On Wed, 25 Jul 2012 16:59:49 -0500
> Timur Tabi wrote:
>
>> Add device tree (dtsi) files for the Freescale P5040 SOC. Since this
>> SOC introduces SEC v5.2, add the dtsi file for that also.
>>
>> Signed-off-by: Timur Tabi
>> ---
>
Alexander Graf wrote:
> After merging the register type check patches from Ben's tree, the
> hv enabled booke implementation ceased to compile.
>
> This patch fixes things up so everyone's happy again.
Is there a defconfig which catches this?
Mikey
>
> Signed-off-by: Alexander Graf
> ---
>
Thanks for all your comments.
I submit the V2 of this patch set which is based on the latest tree.
Please have a review.
Thanks
-Hongtao.
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, July 26, 2012 1:24 AM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; linuxppc-dev@l
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, July 26, 2012 1:26 AM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org; Li Yang-R58472
> Subject: Re: [PATCH 3/6] powerpc/fsl-pci: Determine primary bus by looking
>
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, July 26, 2012 1:24 AM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org; Li Yang-R58472
> Subject: Re: [PATCH 1/6] powerpc/fsl-pci: Unify pci/pcie initialization
> c
Hello,
A gentle reminder!
Any comments are appreciated.
Regards,
Shengzhou
> -Original Message-
> From: Liu Shengzhou-B36685
> Sent: Wednesday, July 18, 2012 2:07 PM
> To: bhelg...@google.com; linux-...@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org; Liu Shengzhou-B36685
> Subjec
From: Ananth N Mavinakayanahalli
Add thread_struct.trap_nr and use it to store the last exception
the thread experienced. In this patch, we populate the field at
various places where we force_sig_info() to the process.
This is also used in uprobes to determine if the probed instruction
caused an
From: Ananth N Mavinakayanahalli
This is the port of uprobes to powerpc. Usage is similar to x86.
[root@ ~]# ./bin/perf probe -x /lib64/libc.so.6 malloc
Added new event:
probe_libc:malloc(on 0xb4860)
You can now use it in all perf tools, such as:
perf record -e probe_libc:mal
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