RE: [PATCH] P1021: set IReady in QE Microcode Upload

>Kokoris, Ioannis wrote: >> Hi, >> >> QE Microcode Initialization using qe_upload_microcode() does not work >> on P1021 if the IRAM-Ready register is not set after the microcode >> upload. This patch adds a definition for the "I-RAM Ready" register and >> sets it uppon microcode upload completion.

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Re: [PATCH 4/5, v3] powerpc/8xxx: Update device tree bus probe for new RapidIO node binding

On 11/12/2011 06:02 AM, Liu Gang wrote: > From: Kai Jiang > > Update of_platform_bus_probe() RapidIO node to be compitable with > new RapidIO dts compatible property. > > Signed-off-by: Kai Jiang > Signed-off-by: Kumar Gala > --- > arch/powerpc/platforms/85xx/corenet_ds.c |2 +- > arch/

Re: [PATCH 4/5, v3] powerpc/8xxx: Update device tree bus probe for new RapidIO node binding

On 11/14/2011 11:35 AM, Scott Wood wrote: > On 11/12/2011 06:02 AM, Liu Gang wrote: >> From: Kai Jiang >> >> Update of_platform_bus_probe() RapidIO node to be compitable with >> new RapidIO dts compatible property. >> >> Signed-off-by: Kai Jiang >> Signed-off-by: Kumar Gala >> --- >> arch/power

[GIT PULL] SRIO powerpc compile fix.

This fixes a compile regression in powerpc's serial rapidio, caused by the module.h split. It wasn't seen in defconfig/linux-next builds since it isn't enabled anywhere by default. Thanks, Paul. The following changes since commit 1ea6b8f48918282bdca0b32a34095504ee65bab5: Linux 3.2-rc1 (2011-

Re: [PATCH 3/5] treewide: Remove useless NORET_TYPE macro and uses

On Thu, Nov 10, 2011 at 10:41, Joe Perches wrote: > It's a very old and now unused prototype marking > so just delete it. > > Neaten panic pointer argument style to keep checkpatch quiet. > > Signed-off-by: Joe Perches For the m68k parts: Acked-by: Geert Uytterhoeven Gr{oetje,eeting}s,      

Re: [PATCH 4/5] treewide: Convert uses of ATTRIB_NORETURN to __noreturn

On Thu, Nov 10, 2011 at 10:41, Joe Perches wrote: > Use the more commonly used __noreturn instead of ATTRIB_NORETURN. > > Signed-off-by: Joe Perches For the m68k parts: Acked-by: Geert Uytterhoeven Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linu

[PATCH] powerpc/44x: Fix typos '47x' and 'CONFIG_47x'

Commit 674bfa4855 ("powerpc/44x: Kexec support for PPC440X chipsets") used the Kconfig symbol '47x', and the macro 'CONFIG_47x'. Neither exist. These should have been 'PPC_47x' and 'CONFIG_PPC_47x'. Fix these typos. Also fix a related preprocessor check at the top of kexec.h. Signed-off-by: Paul

[PATCH] powerpc: Copy down exception vectors after feature fixups

kdump fails because we try to execute an HV only instruction. Feature fixups are being applied after we copy the exception vectors down to 0 so they miss out on any updates. We have always had this issue but it only became critical in v3.0 when we added CFAR support (breaks POWER5) and v3.1 when

[PATCH] powerpc: panic if we can't instantiate RTAS

I had to debug a strange situation where all manner of things were failing. SMT threads, storage and network were all completely broken. The root cause was we couldn't find enough memory to instantiate RTAS - this was a network install so the initrd was huge. Instead of limping along and failing

Re: [PATCH] powerpc/44x: Fix typos '47x' and 'CONFIG_47x'

On 11/15/11 04:00, Paul Bolle wrote: Commit 674bfa4855 ("powerpc/44x: Kexec support for PPC440X chipsets") used the Kconfig symbol '47x', and the macro 'CONFIG_47x'. Neither exist. These should have been 'PPC_47x' and 'CONFIG_PPC_47x'. Fix these typos. Thanks for catching this. I have already s

[RFC PATCH 0/2] powerpc: CPU cache op cleanup

Ok, so I have a work-in-progress patch for cleaning up the CPU cache handling, and I'd like some comments on the approach. It's not really split up, and it's kind of a huge patch because it tries to tackle a lot of things at once. Unfortunately, I'm having a hard time finding good clean places to

[RFC PATCH 1/2] powerpc: Remove duplicate cacheable_memcpy/memzero functions

These functions are only used from one place each. If the cacheable_* versions really are more efficient, then those changes should be migrated into the common code instead. NOTE: The old routines are just flat buggy on kernels that support hardware with different cacheline sizes. Signed-o

[RFC PATCH 2/2] WIP: PowerPC cache cleanup

This badly needs breaking up, and a better changelog... oh well... The big changes: * The "ppc64_caches" structure is now "powerpc_caches" and is used on both PPC32 and PPC64. I hated staring at the pages and pages of assembly code, so nearly all of the functions are now C with tiny snippe

Re: [RFC PATCH 00/17] powerpc/e500: separate e500 from e500mc

Moffett, Kyle D wrote: >the PPC Book-E spec documents that the pagesize is an even multiple > of the cacheline size and the cachelines are always page-aligned. cachelines are page aligned? -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-

[UPDATED] [PATCH v3 1/8] [44x] Fix typo in KEXEC CONFIG dependency

Kexec is not supported on 47x. 47x is a variant of 44x with slightly different MMU and SMP support. There was a typo in the config dependency for KEXEC. This patch fixes the same. Signed-off-by: Suzuki K. Poulose Signed-off-by: Paul Bolle Cc: Kumar Gala Cc: Josh Boyer Cc: linux ppc

Re: [RFC PATCH 00/17] powerpc/e500: separate e500 from e500mc

On Nov 10, 2011, at 23:40, Benjamin Herrenschmidt wrote: > On Thu, 2011-11-10 at 18:38 -0600, Moffett, Kyle D wrote: >> (2) Make the ppc64_caches struct apply to ppc32 as well, and >> preinitialize it with a minimum value used by any platform being >> compiled in (for "dcbXX"/"icbXX" pur

RE: [PATCH 4/5, v3] powerpc/8xxx: Update device tree bus probe for new RapidIO node binding

Yeah, send binding first should be better for reviewing entire set of patches. Thanks! -Original Message- From: Wood Scott-B07421 Sent: Tuesday, November 15, 2011 1:37 AM To: Liu Gang-B34182 Cc: Li Yang-R58472; Jiang Kai-B18973; linux-ker...@vger.kernel.org; Zang Roy-R61911; alexandre.bo

Re: [RFC PATCH 00/17] powerpc/e500: separate e500 from e500mc

On Mon, Nov 14, 2011 at 21:41, Tabi Timur-B04825 wrote: > Moffett, Kyle D wrote: >>the PPC Book-E spec documents that the pagesize is an even multiple >> of the cacheline size and the cachelines are always page-aligned. > > cachelines are page aligned? Whoops, good catch. That should have been:

Re: [PATCH] net: fsl_pq_mdio: fix non tbi phy access

Hi Andy, On Mon, Nov 14, 2011 at 09:04:47PM +, Fleming Andy-AFLEMING wrote: > Well, this got applied quickly, so I guess I can't NAK, but this requires > discussion. > > On Nov 14, 2011, at 0:22, "Baruch Siach" wrote: > > > Since 952c5ca1 (fsl_pq_mdio: Clean up tbi address configuration) .