On 11/03/11 05:06, Josh Poimboeuf wrote:
On Tue, 2011-10-25 at 17:23 +0530, Suzuki K. Poulose wrote:
The following patch implements the dynamic relocation processing for
PPC32 kernel. relocate() accepts the target virtual address and relocates
the kernel image to the same.
Hi Suzuki,
Thanks
From: Li Yang
The timebase sync is not only necessary when using KEXEC. It should also
be used by normal boot up and cpu hotplug. Remove the ifdef added by
the KEXEC patch.
Signed-off-by: Jin Qing
Signed-off-by: Li Yang
---
arch/powerpc/platforms/85xx/smp.c |2 --
1 files changed, 0 inser
From: Li Yang
Add support to disable and re-enable individual cores at runtime
on MPC85xx/QorIQ SMP machines. Currently support e500 core.
MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off.
This patch uses the boot page from bootloader to boot core at runtime.
It supports 32-bi
From: Li Yang
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running
While in deep sleep PM mode, add
From: Li Yang
Signed-off-by: Li Yang
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 63 +++
1 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
From: Li Yang
Some 85xx silicons like MPC8536 and P1022 has the JOG PM feature.
The patch adds the support to change CPU frequency using the standard
cpufreq interface. Add the all PLL ratio core support. The ratio CORE
to CCB can 1:1, 1.5, 2:1, 2.5:1, 3:1, 3.5:1 and 4:1
Signed-off-by: Dave Liu
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu
Signed-off-by: Li Yang
Signed-off-by: Jin Qing
Signed-off-by: Zhao Chenhui
---
arch/powerpc/sysdev/fsl_pmc.c | 67 ++
On certain chip like MPC8536 and P1022, system can be waked up from
sleep by user defined packet. This patch implements that system waked
up by ARP request packet or unicast patcket to this station.
When entering suspend state, the gianfar driver sets receive queue
filer table to filter all of pac
On Thu, Nov 03, 2011 at 02:51:22PM +1100, Michael Ellerman wrote:
> There is some code in place to support multiple MSI, but only in the
> generic code (drivers/pci/msi.c), and I'm not sure if it's complete.
> There is no arch support, for any arch AFAIK, and certainly not for
> powerpc.
I think t
On Thu, Nov 3, 2011 at 5:12 PM, Robert Sciuk wrote:
> lim_r: gpio@e8 {
> compatible = "nxp,pca9539";
> reg = <0xe8>;
> #gpio-cells = <2>;
> gpio-contr
> > It appears that I'm not correctly creating the pca9539 nodes as of
> yet (I'll be adding the phandles shortly). Any pointers for pca9539
> driver nodes would be appreciated, as I took these from a similar tree,
> but not the 95xx driver. I'll match them up with the code in the
> morning ...
On 11/04/2011 07:29 AM, Zhao Chenhui wrote:
> From: Li Yang
>
> The timebase sync is not only necessary when using KEXEC. It should also
> be used by normal boot up and cpu hotplug. Remove the ifdef added by
> the KEXEC patch.
The KEXEC patch didn't just add the ifdef, it also added the initiali
> >
> > I *believe* you are not supposed to create separate nodes for reading
> > and writing. I know that's how I2C works, but I think the I2C layer
> > takes care of that for you.
> >
> > If you look at other device trees, you'll see they only have one node
> > for any particular I2C device.
> >
On 11/04/2011 07:31 AM, Zhao Chenhui wrote:
> From: Li Yang
>
> Add support to disable and re-enable individual cores at runtime
> on MPC85xx/QorIQ SMP machines. Currently support e500 core.
>
> MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off.
> This patch uses the boot page
On 11/04/2011 07:33 AM, Zhao Chenhui wrote:
> +/* Cast the ccsrbar to 64-bit parameter so that the assembly
> + * code can be compatible with both 32-bit & 36-bit */
> +extern void mpc85xx_enter_deep_sleep(u64 ccsrbar, u32 powmgtreq);
/*
* Please use proper
* Linux multi-line comment format.
*/
Hi Zhao,
From: Li Yang
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the proce
On Nov 4, 2011, at 12:33 PM, Scott Wood wrote:
> On 11/04/2011 07:29 AM, Zhao Chenhui wrote:
>> From: Li Yang
>>
>> The timebase sync is not only necessary when using KEXEC. It should also
>> be used by normal boot up and cpu hotplug. Remove the ifdef added by
>> the KEXEC patch.
>
> The KEXEC
On 11/04/2011 02:33 PM, Kumar Gala wrote:
>
> On Nov 4, 2011, at 12:33 PM, Scott Wood wrote:
>
>> On 11/04/2011 07:29 AM, Zhao Chenhui wrote:
>>> From: Li Yang
>>>
>>> The timebase sync is not only necessary when using KEXEC. It should also
>>> be used by normal boot up and cpu hotplug. Remove t
On 11/04/2011 07:36 AM, Zhao Chenhui wrote:
> From: Li Yang
>
> Some 85xx silicons like MPC8536 and P1022 has the JOG PM feature.
>
> The patch adds the support to change CPU frequency using the standard
> cpufreq interface. Add the all PLL ratio core support. The ratio CORE
> to CCB can 1:1, 1.
On 11/04/2011 07:36 AM, Zhao Chenhui wrote:
> From: Li Yang
>
> Signed-off-by: Li Yang
> ---
> .../devicetree/bindings/powerpc/fsl/pmc.txt| 63 +++
> 1 files changed, 36 insertions(+), 27 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.
On 11/04/2011 03:05 PM, Scott Wood wrote:
> On 11/04/2011 07:36 AM, Zhao Chenhui wrote:
>> + "fsl,p1022-pmc" should be listed for any chip whose PMC is
>> + compatible, and implies lossless Ethernet capability during sleep.
>>
>>"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
On 11/04/2011 07:40 AM, Zhao Chenhui wrote:
> diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> index 2c6be03..543e36c 100644
> --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> +++ b/Documentation/devicetr
On 11/04/2011 04:11 PM, Scott Wood wrote:
> On 11/04/2011 07:40 AM, Zhao Chenhui wrote:
>> static int gfar_suspend(struct device *dev)
>> {
>> @@ -1268,9 +1443,17 @@ static int gfar_suspend(struct device *dev)
>> struct gfar __iomem *regs = priv->gfargrp[0].regs;
>> unsigned long flags;
On 11/04/2011 07:39 AM, Zhao Chenhui wrote:
> @@ -45,6 +46,72 @@ static int has_lossless;
> * code can be compatible with both 32-bit & 36-bit */
> extern void mpc85xx_enter_deep_sleep(u64 ccsrbar, u32 powmgtreq);
>
> +#ifdef CONFIG_FSL_PMC
> +/**
> + * pmc_enable_wake - enable OF device as wa
On Fri, Nov 4, 2011 at 7:39 AM, Zhao Chenhui wrote:
> + if (!pmc_regs) {
> + printk(KERN_WARNING "PMC is unavailable\n");
Use pr_warn() and the other pr_xxx functions.
> + pmcdr_mask = (u32 *)of_get_property(clk_np, "fsl,pmcdr-mask", NULL);
The typecast is unnecessary
On Thu, Nov 03, 2011 at 09:14:44AM -0400, John Stultz wrote:
> On Thu, 2011-11-03 at 11:59 +1100, Anton Blanchard wrote:
> > plain text document attachment (clock3)
> > Use clocksource_register_hz which calculates the shift/mult
> > factors for us.
> >
> > Signed-off-by: Anton Blanchard
> > ---
>
On Fri, Nov 04, 2011 at 02:19:36PM -0400, Robert Sciuk wrote:
> > >
> > > I *believe* you are not supposed to create separate nodes for reading
> > > and writing. I know that's how I2C works, but I think the I2C layer
> > > takes care of that for you.
> > >
> > > If you look at other device trees,
Hi Zhao,
From: Li Yang
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the proce
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