Implement perf-events based hw-breakpoint interfaces for PowerPC Book III S
processors. These interfaces help arbitrate requests from various users and
schedules them as appropriate.
Signed-off-by: K.Prasad
---
arch/powerpc/Kconfig |1
arch/powerpc/include/asm/cputable.h
An alignment interrupt may intervene between a DSI/hw-breakpoint exception
and the single-step exception. Enable the alignment interrupt (through
modifications to emulate_single_step()) to notify the single-step exception
handler for proper restoration of hw-breakpoints.
Signed-off-by: K.Prasad
-
On Mon, May 24, 2010 at 04:04:19PM +0530, K.Prasad wrote:
> A signal delivered between a hw_breakpoint_handler() and the
> single_step_dabr_instruction() will not have the breakpoint active during
> signal handling (since breakpoint will not be restored through single-stepping
> due to absence of
A signal delivered between a hw_breakpoint_handler() and the
single_step_dabr_instruction() will not have the breakpoint active during
signal handling (since breakpoint will not be restored through single-stepping
due to absence of MSR_SE bit on the signal frame). Enable breakpoints before
signal d
Hi All,
Here's a quick release of the next version of the patchset with a
small, yet significant changelog.
Please let me know the comments, if any.
Changelog - ver XX
(Version XIX: linuxppc-dev ref: 20100524040137.ga20...@in.ibm.com)
- Non task-bound breakpoints will
Certain architectures (such as PowerPC Book III S) have a need to cleanup
data-structures before the breakpoint is unregistered. This patch introduces
an arch-specific hook in release_bp_slot() along with a weak definition in
the form of a stub funciton.
Signed-off-by: K.Prasad
---
kernel/hw_bre
On Thu, May 20, 2010 at 11:10:03PM +1000, Paul Mackerras wrote:
> On Thu, May 20, 2010 at 09:36:03AM +0530, K.Prasad wrote:
>
(Had this mail composed along with the patchset...but mail server issues
caused delay in sending this...)
Hi Paul,
While we continue to discuss some of the design
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if i
On Mon, May 24, 2010 at 10:25 AM, Martyn Welch wrote:
> Currently the irqs for the i8042, which historically provides keyboard and
> mouse (aux) support, is hardwired in the driver rather than parsing the
> dts. This patch modifies the powerpc legacy IO code to attempt to parse
> the device tree
From: Li Yang
In CONFIG_PTE_64BIT the PTE format has unique permission bits for user
and supervisor execute. However on !CONFIG_PTE_64BIT we overload the
supervisor bit to imply user execute with _PAGE_USER set. This allows
us to use the same permission check mask for user or supervisor code on
When we build with ftrace enabled its possible that loadcam_entry would
have used the stack pointer (even though the code doesn't need it). We
call loadcam_entry in __secondary_start before the stack is setup. To
ensure that loadcam_entry doesn't use the stack pointer the easiest
solution is to j
From: Benjamin Herrenschmidt
We can't just clear the user read permission in book3e pte, because
that will also clear supervisor read permission. This surely isn't
desired. Fix the problem by adding the supervisor read back.
BenH: Slightly simplified the ifdef and applied to ppc64 too
Signed-
On Apr 4, 2010, at 3:19 PM, Sebastian Andrzej Siewior wrote:
> From: Sebastian Andrzej Siewior
>
> This patch only moves the initial entry code which setups the mapping
> from what ever to KERNELBASE into a seperate file. No code change has
> been made here.
>
> Signed-off-by: Sebastian Andrze
On Apr 4, 2010, at 3:19 PM, Sebastian Andrzej Siewior wrote:
> From: Sebastian Andrzej Siewior
>
> During boot we change the mapping a few times until we have a "defined"
> mapping. During this procedure a small 4KiB mapping is created and after
> that one a 64MiB. Currently the offset of the 4
On Apr 4, 2010, at 3:19 PM, Sebastian Andrzej Siewior wrote:
> From: Sebastian Andrzej Siewior
>
> This adds support kexec on FSL-BookE where the MMU can not be simply
> switched off. The code borrows the initial MMU-setup code to create the
> identical mapping mapping. The only difference to t
On Apr 22, 2010, at 3:31 AM, Li Yang wrote:
> In fsl_of_msi_probe(), the virt_msir's chip_data have been stored
> the pointer to struct mpic. We add a struct fsl_msi_cascade_data
> to store the pointer to struct fsl_msi and msir_index in hanler_data.
> Otherwise, the pointer to struct mpic will b
On Apr 22, 2010, at 3:31 AM, Li Yang wrote:
> Put all fsl_msi banks in a linked list. The list of banks then can be
> traversed when allocating new msi interrupts. Also fix failing path
> of fsl_setup_msi_irqs().
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/sy
On Apr 22, 2010, at 3:31 AM, Li Yang wrote:
> Make a single PCIe MSI bank shareable through CAMP OSes. The number of
> MSI used by each core can be configured by dts file.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/sysdev/fsl_msi.c |8 +++-
> 1 files c
On Apr 22, 2010, at 3:31 AM, Li Yang wrote:
> Enable the sharing of MSI interrupt through AMP OSes in the mpc8572ds
> dtses.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts | 15 +--
> arch/powerpc/boot/dts/mpc8572ds_
On Apr 22, 2010, at 3:31 AM, Li Yang wrote:
> Also cleanup the probe function.
>
> Signed-off-by: Li Yang
> ---
> arch/powerpc/sysdev/fsl_msi.c | 36 ++--
> arch/powerpc/sysdev/fsl_msi.h |1 +
> 2 files changed, 31 insertions(+), 6 deletions(-)
applied to ne
On May 14, 2010, at 12:40 AM, Michael Neuling wrote:
> When we are crashing, the crashing/primary CPU IPIs the secondaries to
> turn off IRQs, go into real mode and wait in kexec_wait. While this
> is happening, the primary tears down all the MMU maps. Unfortunately
> the primary doesn't check
On May 24, 2010, at 2:23 PM, Kumar Gala wrote:
>
> On May 14, 2010, at 12:40 AM, Michael Neuling wrote:
>
>> When we are crashing, the crashing/primary CPU IPIs the secondaries to
>> turn off IRQs, go into real mode and wait in kexec_wait. While this
>> is happening, the primary tears down all
In message <04ac722a-97cd-4451-b6ab-f4ac37efa...@kernel.crashing.org> you wrote
:
>
> On May 24, 2010, at 2:23 PM, Kumar Gala wrote:
>
> >=20
> > On May 14, 2010, at 12:40 AM, Michael Neuling wrote:
> >=20
> >> When we are crashing, the crashing/primary CPU IPIs the secondaries =
> to
> >> turn
The following changes since commit 99ec28f183daa450faa7bdad6f932364ae325648:
FUJITA Tomonori (1):
powerpc: Remove unused 'protect4gb' boot parameter
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Andy Fleming (1):
po
On May 21, 2010, at 9:16 AM, Haiying Wang wrote:
> P1021 is a dual e500v2 core based SOC with:
> * 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board)
> * 2 PCIe Controller
> * 1 USB2.0 controller
> * eSDHC, eSPI, I2C, DUART
> * eLBC (NAND, BCSR, PMC0/1)
> * Security Engine (SEC 3.3.2)
> * Quic
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