On Mon, 2009-08-17 at 11:54 +0530, Dipankar Sarma wrote:
> On Sun, Aug 16, 2009 at 11:53:22PM +0200, Peter Zijlstra wrote:
> > On Mon, 2009-08-17 at 01:14 +0530, Balbir Singh wrote:
> > > Agreed, I've tried to come with a little ASCII art to depict your
> > > scenairos graphically
> > >
> > >
> >
On Mon, Aug 17, 2009 at 09:15:57AM +0200, Peter Zijlstra wrote:
> On Mon, 2009-08-17 at 11:54 +0530, Dipankar Sarma wrote:
> > For most parts, we do. The guest kernel doesn't manage the offline
> > CPU state. That is typically done by the hypervisor. However, offline
> > operation as defined now al
On Sun, Aug 16, 2009 at 08:20:17AM +1000, Benjamin Herrenschmidt wrote:
>Hi !
>
>I'd like to rebase powerpc-next ... a few bugs have been found that it
>would be nice to fix in the original patch rather than introducing a
>bisection breakage, and Kumar also just noticed a potentially misleading
>er
The ptrace POKETEXT interface allows a process to modify the text pages of
a child process being ptraced, usually to insert breakpoints via trap
instructions. The kernel eventually calls copy_to_user_page, which in turn
calls __flush_icache_range to invalidate the icache lines for the child
proces
On Sat, Aug 15, 2009 at 02:25:49AM +0400, Anton Vorontsov wrote:
[]
> +#ifdef CONFIG_CPM
> int cpm_command(u32 command, u8 opcode);
> +#else
> +static inline int cpm_command(u32 command, u8 opcode)
> +{
> + return -ENOSYS;
> +}
> +#endif /* CONFIG_CPM */
It appers that fsl_qe_udc.h define
On Mon, Aug 17, 2009 at 01:28:15PM +0530, Dipankar Sarma wrote:
> On Mon, Aug 17, 2009 at 09:15:57AM +0200, Peter Zijlstra wrote:
> > On Mon, 2009-08-17 at 11:54 +0530, Dipankar Sarma wrote:
> > > For most parts, we do. The guest kernel doesn't manage the offline
> > > CPU state. That is typically
On Aug 15, 2009, at 5:20 PM, Benjamin Herrenschmidt wrote:
Hi !
I'd like to rebase powerpc-next ... a few bugs have been found that it
would be nice to fix in the original patch rather than introducing a
bisection breakage, and Kumar also just noticed a potentially
misleading
error in a com
On Thu, Jul 30, 2009 at 04:08:49PM -0400, Josh Boyer wrote:
>>> Ok. So I'm not really all that thrilled with changes to ppcboot.h.
>>> We try to keep this file as much in-sync with U-Boot as we can. Did
>>> your HOTFOOT changes get pulled into upstream U-Boot?
>>
>>Yeah, I thought this may be
On Wed, Aug 12, 2009 at 05:38:47PM -0700, Feng Kan wrote:
>This patch adds support for the AMCC (AppliedMicro) PPC460SX Eiger evaluation
>board.
>
>Signed-off-by: Tai Tri Nguyen
>Acked-by: Feng Kan
>Acked-by: Tirumala Marri
>---
> arch/powerpc/boot/dts/eiger.dts| 421 ++
> a
On Mon, Aug 17, 2009 at 09:41:36AM -0400, Josh Boyer wrote:
>The ptrace POKETEXT interface allows a process to modify the text pages of
>a child process being ptraced, usually to insert breakpoints via trap
>instructions. The kernel eventually calls copy_to_user_page, which in turn
>calls __flush_
Please do, much appreciated.
Thanks
Feng Kan
AMCC Software
On 08/17/2009 08:34 AM, Josh Boyer wrote:
On Wed, Aug 12, 2009 at 05:38:47PM -0700, Feng Kan wrote:
This patch adds support for the AMCC (AppliedMicro) PPC460SX Eiger evaluation
board.
Signed-off-by: Tai Tri Nguyen
Acked-by: Feng
On Wed, Aug 12, 2009 at 11:49 PM, Heiko Schocher wrote:
> Hello Anton,
>
> i am trying to use the arch/powerpc/sysdev/simple_gpio.c driver,
> for accessing some gpios, and found, that u8_gpio_get()
> returns not only a 1 or a 0, instead it returns the real bit
> position from the gpio:
>
> gpio
On Mon, 2009-08-17 at 12:07 -0400, Josh Boyer wrote:
>
> Olof pointed out that we could probably do the iccci before the icbi loop and
> just skip that loop entirely on 44x. This is most certainly valid, but at
> this particular moment I don't have time to try and reproduce the issue with
> an al
This provides a mechanism to allow the perf_counters code to access
user memory in a PMU interrupt routine. Such an access can cause
various kinds of interrupt: SLB miss, MMU hash table miss, segment
table miss, or TLB miss, depending on the processor. This commit
only deals with 64-bit classic/s
This adds support for tracing callchains for powerpc, both 32-bit
and 64-bit, and both in the kernel and userspace, from PMU interrupt
context.
The first three entries stored for each callchain are the NIP (next
instruction pointer), LR (link register), and the contents of the LR
save area in the
On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two
32-bit halves. On SMP we write the higher-order half and then the
lower-order half, with a write barrier between the two halves, but on
UP there was no particular ordering of the writes to the two halves.
This extends the orde
Oops, I missed that patch, sorry.
On Mon, Aug 17, 2009 at 03:18:37PM -0600, Grant Likely wrote:
> On Wed, Aug 12, 2009 at 11:49 PM, Heiko Schocher wrote:
> > Hello Anton,
> >
> > i am trying to use the arch/powerpc/sysdev/simple_gpio.c driver,
> > for accessing some gpios, and found, that u8_gpio_
On Aug 17, 2009, at 6:00 PM, Paul Mackerras wrote:
On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two
32-bit halves. On SMP we write the higher-order half and then the
lower-order half, with a write barrier between the two halves, but on
UP there was no particular ordering
Kumar Gala writes:
> On Aug 17, 2009, at 6:00 PM, Paul Mackerras wrote:
>
> > On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two
> > 32-bit halves. On SMP we write the higher-order half and then the
> > lower-order half, with a write barrier between the two halves, but on
> >
On Tue, Aug 18, 2009 at 07:46:28AM +1000, Benjamin Herrenschmidt wrote:
>On Mon, 2009-08-17 at 12:07 -0400, Josh Boyer wrote:
>>
>> Olof pointed out that we could probably do the iccci before the icbi loop and
>> just skip that loop entirely on 44x. This is most certainly valid, but at
>> this pa
1) It looks like the correct entry in kilauea.dts file should be:
208 IIC1: i...@ef600500 {
209 compatible = "ibm,iic-405ex", "ibm,iic";
210 reg = ;
211 interrupt-parent = <&UIC0>;
212 interrupts = <7 4>;
213
On Mon, 2009-08-17 at 20:16 -0400, Josh Boyer wrote:
>
> You can if you'd like. My biggest concern is getting time to
> recreate. I
> think I'll have time later in the week if you'd like to wait until
> then.
> I simply didn't want to send out a patch that I wasn't sure fixed the
> issue.
>
Tha
Summary: powerpc/405ex: Support cuImage for PPC405EX
Reviewers: Benjmain and linux-ppc
These patch series are used to support cuImage on the kilauea board based on
PPC405ex.
Tested on the amcc kilauea board:
===
...
=> tftp 100 cuImage.kila
To support cuImage, we need to initialize the required sections and
ensure that it is built.
Signed-off-by: Tiejun Chen
---
arch/powerpc/boot/Makefile |3 +-
arch/powerpc/boot/cuboot-kilauea.c | 50
2 files changed, 52 insertions(+), 1 deletion
For cuImage format it's necessary to provide clock fixups since u-boot will
not pass necessary clock frequency into the dtb included into cuImage so we
implement the clock fixups as defined in the technical documentation for the
board and update header file with the basic register definitions.
Please do *not* send mail to both linuxppc-...@ozlabs.org and
linuxppc-...@lists.ozlabs.org. We all end up with two copies :-(
They are the same list.
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
pgp4qi6OjUw4I.pgp
Description: PGP sign
On Tue, 2009-08-18 at 10:28 +0800, Tiejun Chen wrote:
> Summary: powerpc/405ex: Support cuImage for PPC405EX
> Reviewers: Benjmain and linux-ppc
>
> These patch series are used to support cuImage on the kilauea board based on
> PPC405ex.
Thanks
So here's a followup to my discussion about the clock API.
I'm cooking up a patch that replace our current primitive implementation
in arch/powerpc/kernel/clock.c with something along the lines of what I
described. However, I want a bit more churn here on the device-tree
related bits.
So, basical
On Tue, 2009-08-18 at 09:01 +1000, Paul Mackerras wrote:
> This adds support for tracing callchains for powerpc, both 32-bit
> and 64-bit, and both in the kernel and userspace, from PMU interrupt
> context.
> Signed-off-by: Paul Mackerras
Acked-by: Benjamin Herrenschmidt
On Tue, 2009-08-18 at 09:00 +1000, Paul Mackerras wrote:
> This provides a mechanism to allow the perf_counters code to access
> user memory in a PMU interrupt routine. Such an access can cause
> various kinds of interrupt: SLB miss, MMU hash table miss, segment
> table miss, or TLB miss, dependin
On Tue, 2009-08-18 at 09:00 +1000, Paul Mackerras wrote:
> On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two
> 32-bit halves. On SMP we write the higher-order half and then the
> lower-order half, with a write barrier between the two halves, but on
> UP there was no particular
Stephen Rothwell wrote:
> Please do *not* send mail to both linuxppc-...@ozlabs.org and
> linuxppc-...@lists.ozlabs.org. We all end up with two copies :-(
>
> They are the same list.
Sorry for this inconvenient I bring :(
Best Regards
Tiejun
___
Linu
Hello Grant,
Grant Likely wrote:
> On Wed, Aug 12, 2009 at 11:49 PM, Heiko Schocher wrote:
>> Hello Anton,
>>
>> i am trying to use the arch/powerpc/sysdev/simple_gpio.c driver,
>> for accessing some gpios, and found, that u8_gpio_get()
>> returns not only a 1 or a 0, instead it returns the real b
Hello Anton,
Anton Vorontsov wrote:
> Oops, I missed that patch, sorry.
>
> On Mon, Aug 17, 2009 at 03:18:37PM -0600, Grant Likely wrote:
>> On Wed, Aug 12, 2009 at 11:49 PM, Heiko Schocher wrote:
>>> Hello Anton,
>>>
>>> i am trying to use the arch/powerpc/sysdev/simple_gpio.c driver,
>>> for ac
Ben,
The following changes since commit 64f1607ffbbc772685733ea63e6f7f4183df1b16:
Linus Torvalds (1):
Linux 2.6.31-rc6
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/perfcounters.git master
Please pull them into your powerpc-next branch.
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