On Tue, 2009-08-18 at 09:00 +1000, Paul Mackerras wrote: > This provides a mechanism to allow the perf_counters code to access > user memory in a PMU interrupt routine. Such an access can cause > various kinds of interrupt: SLB miss, MMU hash table miss, segment > table miss, or TLB miss, depending on the processor. This commit > only deals with 64-bit classic/server processors, which use an MMU > hash table. 32-bit processors are already able to access user memory > at interrupt time. Since we don't soft-disable on 32-bit, we avoid > the possibility of reentering hash_page or the TLB miss handlers, > since they run with interrupts disabled.
.../... > > Signed-off-by: Paul Mackerras <pau...@samba.org> Acked-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
