On Thu, 2009-02-26 at 20:15 +0100, Michael Guntsche wrote:
> For testing purposes I tried a recent git snapshot and noticed
> that the gianfar driver had problems.
> While the the Gianfar was detected
> [...]
> trying to up either of the devices gave me
>
> [8.724818] m...@24520:01 not found
On Wed, 4 Mar 2009 20:46:58 +0300
Anton Vorontsov wrote:
> On Sat, Feb 21, 2009 at 04:57:57PM +0100, Pierre Ossman wrote:
> >
> > We can most likely do some micro-optimisation do make the compare part
> > cheaper, but the point was to avoid a function call for all the
> > properly implemented co
On Wed, 4 Mar 2009 20:49:17 +0300
Anton Vorontsov wrote:
> On Sat, Feb 21, 2009 at 04:58:21PM +0100, Pierre Ossman wrote:
> > Just modify the if-clause and
> > things will work.
>
> That would look horrid...
>
> if ((!(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
>
On Wed, 4 Mar 2009 20:48:45 +0300
Anton Vorontsov wrote:
> But I see the point of confusion... Instead of teaching
> "SDHCI core" to work with 32 bits hosts, we'd better handle this
> in the eSDHC part, in the accessors.
>
> This is relatively trivial and should not cause much overhead
> (at lea
On Wed, 4 Mar 2009 20:47:44 +0300
Anton Vorontsov wrote:
>
> I'll get rid of this particular patch, and put some BLOCK_SIZE
> magic into the writew accessor (to clean the DMA bits) instead.
>
> Though, I'll prepare another patch to force blksz to 2048, since
> eSDHC specifies "3" in the blksz c
On Thu, 5 Mar 2009 23:28:50 +0300
Anton Vorontsov wrote:
> This patch adds a new driver: sdhci-of. The driver is similar to
> the sdhci-pci, it contains common probe code, and controller-specific
> ops and quirks.
>
> So far there are only Freescale eSDHC ops and quirks.
>
> Signed-off-by: Anto
On Fri, Mar 6, 2009 at 12:49 AM, Liu Dave-R63238 wrote:
> could you try to set '1' to DMA description bit3?
Dave,
I'm looking at the 8315e reference manual. What is "DMA description bit 3"?
--
Timur Tabi
Linux kernel developer at Freescale
___
Linux
On Sat, 7 Mar 2009 08:14:41 -0700 (MST)
"Eddie Dawydiuk" wrote:
> On another note, can you tell me/point me to some documentation on
> how to get a unique machine ID for a new board?
Do you mean the model in the dts, like "amcc,yosemite"? You just pick
one.
It is just company name, board name.
Hi,
I'm experiencing a strange problem with ethernet on custom
405EXr based board with 10/100 Micrel PHY in MII mode. I ran
u-boot 2009.01 and linux-2.6.27. In u-boot ethernet works flawlessly.
I didn't have to add any u-boot code to initialize the PHY. In linux
ethernet works only if there was s
Hi,
I tried to download the linux-2.6-xlnx from
git://git.xilinx.com/linux-2.6-xlnx.git.
It seems that the git server of Xilinx was down, so I cannot connect to it.
I also tried to download the
git://git.secretlab.ca/git/linux-2.6-virtex.git.
But it shows that:
last change
Fri,
Timur,
See the section 14.7.1 DMA Description Format at page 14-112
of MPC8315ERM rev.1.
> -Original Message-
> From: timur.t...@gmail.com [mailto:timur.t...@gmail.com] On
> Behalf Of Tabi Timur-B04825
> Sent: Sunday, March 08, 2009 11:20 PM
> To: Liu Dave-R63238
> Cc: Ben Menchaca; lin
Hi Ben,
The second issue. you told me "some hosts" has problem,
and some hosts worked well.
what is the problem-hosts?
The issue seems like the hosts did set the NO SNOOP attribute
bit at TLP.
The PEX_DEVICE_CONTROL is standard PCI configuration space
register, it controls the behavior of t
Hi Ben,
The second issue. you told me "some hosts" has problem,
and some hosts worked well.
what is the problem-hosts?
The issue seems like the hosts did set the NO SNOOP attribute
bit at TLP.
The PEX_DEVICE_CONTROL is standard PCI configuration space
register, it controls the behavior of t
The only problem host found so far is a newer Asus 970FX motherboard,
regardless of OS.
We are seeing that some time after LTSSM finishes, but long before OS load,
our PEX_DEVICE_CONTROL register is changed. On the "working" motherboards,
NO_SNOOP is enabled; if I read the spec correctly, this me
Hello All,
I have mpc8313erdb eval board and kernel 2..6.20 on it. I have written
GPIO driver and have enabled Async Notification (SIGIO)
In the driver I am generating interrupt whenever the status of GPIO
pin (GPIO 2) changes, this part is working correct (as soon as the
GPIO pin status changes
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