On 06/17/2013 12:15:36 AM, Lian Minghuan-b31939 wrote:
On 06/15/2013 06:10 AM, Scott Wood wrote:
On 06/14/2013 02:15:58 AM, Minghuan Lian wrote:
For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. For the
first register, when
On 06/15/2013 06:10 AM, Scott Wood wrote:
On 06/14/2013 02:15:58 AM, Minghuan Lian wrote:
For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. For the
first register, when using MSIIR we will get the irqs 0x0 0x1 0x2
...0x1f, bu
On 06/14/2013 02:15:58 AM, Minghuan Lian wrote:
For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. For the
first register, when using MSIIR we will get the irqs 0x0 0x1 0x2
...0x1f, but when using MSIIR1, the irqs are 0x0 0x10
