Josh Boyer wrote:
> I have no idea about FSL cores, but the 4xx maximum value selects TBU
> bit 31. When that bit flips is going to be determined by the speed of
> the clock driving TB. Most of the 4xx implementations I have seen use
> the CPU clock, so to take the example from the 44x user manu
On Mon, Jul 16, 2012 at 4:28 PM, Tabi Timur-B04825 wrote:
> On Fri, Jul 13, 2012 at 7:25 AM, Josh Boyer wrote:
>
>> Right now, if the option is not set we call booke_wdt_disable which
>> indeed does not actually _disable_ the WDT, but it does set the timer
>> period to the maxium value. We could
On Sun, Jul 15, 2012 at 9:07 PM, Lu.Jiang wrote:
>
> Since the ppc44x's watch dog can not reset by software, such operation only
> set the timeout value(WDTP) to minimum, and cause the system reboot
> immediately.
It's supposed to set it to the maximum. That's what WDTP_MASK is
supposed to do.
On Fri, Jul 13, 2012 at 7:25 AM, Josh Boyer wrote:
> Right now, if the option is not set we call booke_wdt_disable which
> indeed does not actually _disable_ the WDT, but it does set the timer
> period to the maxium value. We could go one step further and implement
> a simple timer that pops and
On 07/15/2012 09:07 PM, Lu.Jiang wrote:
> 于 2012年07月13日 19:50, Kumar Gala 写道:
>> On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:
>>
>>> On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
>>> of timer can not reset by software after set to a non-zero value.
>>> Which means software can
于 2012年07月13日 19:50, Kumar Gala 写道:
On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:
On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
of timer can not reset by software after set to a non-zero value.
Which means software can not reset the timeout behaviour of watchdog timer.
This
On Jul 13, 2012, at 7:25 AM, Josh Boyer wrote:
> On Fri, Jul 13, 2012 at 7:50 AM, Kumar Gala wrote:
>>
>> On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:
>>
>>> On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
>>> of timer can not reset by software after set to a non-zero value.
On Fri, Jul 13, 2012 at 7:50 AM, Kumar Gala wrote:
>
> On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:
>
>> On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
>> of timer can not reset by software after set to a non-zero value.
>> Which means software can not reset the timeout behavio
On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:
> On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
> of timer can not reset by software after set to a non-zero value.
> Which means software can not reset the timeout behaviour of watchdog timer.
>
> This patch selects WATCHDOG_NOWA
