On Mon, 2009-10-05 at 11:49 -0400, Mike Nuss wrote:
>
> PS: Is top posting customary on this list? I'm used to bottom posting;
> let me know if I'm doing it wrong.
No you are right but if we were going to have a go at everybody who
does top-posting, we would never finish :-)
Cheers,
Ben.
Mikhail Zolotaryov wrote:
> Hi Mike,
>
> you wrote:
> "Row address bits : 13
> DDR0_02 = 0x020C0E01
> DDR0_42 = 0x0006"
>
> Register values above define that memory has 14 row address bits. The
> correct setting is (for CAS Latency = 3):
> DDR0_42 = 0x0106
>
> Best regards,
> Mikhail Zol
Hi Mike,
you wrote:
"Row address bits : 13
DDR0_02 = 0x020C0E01
DDR0_42 = 0x0006"
Register values above define that memory has 14 row address bits. The
correct setting is (for CAS Latency = 3):
DDR0_42 = 0x0106
Best regards,
Mikhail Zolotaryov
Mike Nuss wrote:
(top-posting correcte
AFAIK, u-boot just writes pre-defined values to the memory controller
registers. It doesn't do any chiptype/memsize detection. These values
are set for Sequoia and may not suite your board. So you probably need
to adjust the u-boot to make linux detect the memory size correctly.
Thanks,
Val.
Valentine wrote:
> AFAIK, u-boot just writes pre-defined values to the memory controller
> registers. It doesn't do any chiptype/memsize detection. These values
> are set for Sequoia and may not suite your board. So you probably need
> to adjust the u-boot to make linux detect the memory size corre
(top-posting corrected)
Mikhail Zolotaryov wrote:
> Mike Nuss wrote:
>> There was a fix a while back called "Correct memory size calculation
>> for Denali based boards" that corrected the data width detection in
>> the 4xx bootwrapper.
>>
>> This seems to have had the unintended consequence of e
Hi Mike,
Address width calculation is based on the DDR-controller configuration
set by the bootloader. It would be helpful for further discussion if you
could send DDR0_00..DDR0_44 register values and memory configuration
used (no of banks, bank size, I/O width) to check calculations. Thanks.
