Mikhail Zolotaryov wrote: > Hi Mike, > > you wrote: > "Row address bits : 13 > DDR0_02 = 0x020C0E01 > DDR0_42 = 0x00000006" > > Register values above define that memory has 14 row address bits. The > correct setting is (for CAS Latency = 3): > DDR0_42 = 0x01000006 > > Best regards, > Mikhail Zolotaryov >
Thank you! It was a bug in U-Boot (they were encoding that register incorrectly). I'll submit a patch to them. Mike _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
