On Thu, 11 Dec 2008 07:03:57 +1100
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
>
> > > We still leave G=1 on the linear mapping for now, we need to
> > > stop over-mapping RAM to be able to remove it.
> >
> > Hm. Over-mapping it has the nice advantage that we use as few pinned
> > TLB ent
> > We still leave G=1 on the linear mapping for now, we need to
> > stop over-mapping RAM to be able to remove it.
>
> Hm. Over-mapping it has the nice advantage that we use as few pinned
> TLB entries as possible. For 440x6 cores with more than 256 MiB of
> DRAM, you could theoretically use a
On Wed, 10 Dec 2008 16:50:50 +1100
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
> After discussing with chip designers, it appears that it's not
> necessary to set G everywhere on 440 cores. The various core
> errata related to prefetch should be sorted out by firmware by
> disabling icache p
After discussing with chip designers, it appears that it's not
necessary to set G everywhere on 440 cores. The various core
errata related to prefetch should be sorted out by firmware by
disabling icache prefetching in CCR0. We add the workaround to
the kernel however just in case ld firmwares
