On Wed, 10 Dec 2008 16:50:50 +1100 Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
> After discussing with chip designers, it appears that it's not > necessary to set G everywhere on 440 cores. The various core > errata related to prefetch should be sorted out by firmware by > disabling icache prefetching in CCR0. We add the workaround to > the kernel however just in case oooold firmwares don't do it. > > This is valid for -all- 4xx core variants. Later ones hard wire > the absence of prefetch but it doesn't harm to clear the bits > in CCR0 (they should already be cleared anyway). > > We still leave G=1 on the linear mapping for now, we need to > stop over-mapping RAM to be able to remove it. Hm. Over-mapping it has the nice advantage that we use as few pinned TLB entries as possible. For 440x6 cores with more than 256 MiB of DRAM, you could theoretically use a single 1GiB TLB entry to map all kernel DRAM. Do you think the trade-offs of allowing speculative accesses are worth the increased TLB pressure? Large base pages will help with that in some workloads, but others are still going to be TLB constrained. I know, I'm probably paranoid. But changing things like this around without some kind of benchmark data or testcase to make sure we aren't making it worse gives me the heebee-geebees. josh _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
