day, June 19, 2012 12:47 AM
>>>> To: Sethi Varun-B16395
>>>> Cc: Kumar Gala; Wood Scott-B07421; Linuxppc-dev@lists.ozlabs.org
>>>> Subject: Re: [PATCH 4/4] powerpc/mpic: FSL MPIC error interrupt
>> support.
>>>>
>>>> On 06/18/2012 02
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, June 19, 2012 12:53 AM
> To: Sethi Varun-B16395
> Cc: Wood Scott-B07421; Kumar Gala; Linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 4/4] powerpc/mpic: FSL MPIC error interrupt support.
>
> On 06
On 06/18/2012 02:19 PM, Sethi Varun-B16395 wrote:
>
>
>> -Original Message-
>> From: Wood Scott-B07421
>> Sent: Tuesday, June 19, 2012 12:47 AM
>> To: Sethi Varun-B16395
>> Cc: Kumar Gala; Wood Scott-B07421; Linuxppc-dev@lists.ozlabs.org
>> Subje
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, June 19, 2012 12:47 AM
> To: Sethi Varun-B16395
> Cc: Kumar Gala; Wood Scott-B07421; Linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 4/4] powerpc/mpic: FSL MPIC error interrupt support.
>
> On 06
On 06/18/2012 02:12 PM, Sethi Varun-B16395 wrote:
>
>
+/*
> + * Error interrupt registers
> + */
> +
> +#define MPIC_ERR_INT_BASE0x3900
> +#define MPIC_ERR_INT_EISR0x
> +#define MPIC_ERR_INT_EIMR0x0010
> +
> #define MPIC_MAX_IRQ_SOU
>>> +/*
> >>> + * Error interrupt registers
> >>> + */
> >>> +
> >>> +#define MPIC_ERR_INT_BASE0x3900
> >>> +#define MPIC_ERR_INT_EISR0x
> >>> +#define MPIC_ERR_INT_EIMR0x0010
> >>> +
> >>> #define MPIC_MAX_IRQ_SOURCES 2048
> >>> #define MPIC_MAX_CPUS
On Mar 27, 2012, at 2:07 PM, Scott Wood wrote:
> On 03/27/2012 08:59 AM, Kumar Gala wrote:
>>
>> On Mar 27, 2012, at 7:17 AM, Varun Sethi wrote:
>>
>>> All SOC device error interrupts are muxed and delivered to the core as a
>>> single
>>> MPIC error interrupt. Currently all the device drivers
On 03/27/2012 08:59 AM, Kumar Gala wrote:
>
> On Mar 27, 2012, at 7:17 AM, Varun Sethi wrote:
>
>> All SOC device error interrupts are muxed and delivered to the core as a
>> single
>> MPIC error interrupt. Currently all the device drivers requiring access to
>> device
>> errors have to registe
On Mar 27, 2012, at 7:17 AM, Varun Sethi wrote:
> All SOC device error interrupts are muxed and delivered to the core as a
> single
> MPIC error interrupt. Currently all the device drivers requiring access to
> device
> errors have to register for the MPIC error interrupt as a shared interrupt.
All SOC device error interrupts are muxed and delivered to the core as a single
MPIC error interrupt. Currently all the device drivers requiring access to
device
errors have to register for the MPIC error interrupt as a shared interrupt.
With this patch we add interrupt demuxing capability in the
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