[mailto:ga...@kernel.crashing.org]
>>>> Sent: Friday, August 03, 2012 6:49 PM
>>>> To: Sethi Varun-B16395
>>>> Cc: linuxppc-dev@lists.ozlabs.org; Hamciuc Bogdan-BHAMCIU1
>>>> Subject: Re: [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error interrupt
&
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Saturday, August 04, 2012 12:55 AM
> To: Sethi Varun-B16395
> Cc: linuxppc-dev@lists.ozlabs.org; Hamciuc Bogdan-BHAMCIU1
> Subject: Re: [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error i
gdan-BHAMCIU1
>> Subject: Re: [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error interrupt
>> support.
>>
>>
>> On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
>>
>>> All SOC device error interrupts are muxed and delivered to the core as
>>> a si
ciuc Bogdan-BHAMCIU1; linuxppc-
>> d...@lists.ozlabs.org
>> Subject: Re: [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error interrupt
>> support.
>>
>>
>> On Aug 3, 2012, at 11:44 AM, Scott Wood wrote:
>>
>>> On 08/03/2012 08:19 AM, Kumar Gala wrote:
>>>>
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Saturday, August 04, 2012 12:43 AM
> To: Wood Scott-B07421
> Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH 3/3 v3] powerpc
On Aug 3, 2012, at 11:44 AM, Scott Wood wrote:
> On 08/03/2012 08:19 AM, Kumar Gala wrote:
>>
>> On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
>>> + /* ioremap'ed base for error interrupt registers */
>>> + u32 __iomem *err_regs;
>>> + /* error interrupt config */
>>> + u32
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Friday, August 03, 2012 6:49 PM
> To: Sethi Varun-B16395
> Cc: linuxppc-dev@lists.ozlabs.org; Hamciuc Bogdan-BHAMCIU1
> Subject: Re: [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error i
On 08/03/2012 08:19 AM, Kumar Gala wrote:
>
> On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
>> +/* ioremap'ed base for error interrupt registers */
>> +u32 __iomem *err_regs;
>> +/* error interrupt config */
>> +u32 err_int_config_done;
>> +
>
> Is this r
On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
> All SOC device error interrupts are muxed and delivered to the core as a
> single
> MPIC error interrupt. Currently all the device drivers requiring access to
> device
> errors have to register for the MPIC error interrupt as a shared interrupt.
All SOC device error interrupts are muxed and delivered to the core as a single
MPIC error interrupt. Currently all the device drivers requiring access to
device
errors have to register for the MPIC error interrupt as a shared interrupt.
With this patch we add interrupt demuxing capability in the
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