On Wed, 2011-06-22 at 16:24 -0500, Scott Wood wrote:
>
> This saved another 1% or so. I don't think TLB_SCRATCH needs to be saved
> by crit/debug/mcheck -- they shouldn't be taking TLB misses, at least
> in the bolted case.
The code they call will (think accessing the UART)
> Even non-bolted,
On Sat, 18 Jun 2011 08:44:29 +1000
Benjamin Herrenschmidt wrote:
> Can't you just re-org the PACA instead ? (with a comment) ? Or at least
> if you want to keep it that way, put the cache line explanation in a
> comment somewhere.
OK.
> > > > +.macro tlb_prolog_bolted addr
> > > > + mtspr
On Fri, 2011-06-17 at 11:32 -0500, Scott Wood wrote:
> On Fri, 17 Jun 2011 12:00:50 +1000
> Benjamin Herrenschmidt wrote:
>
> > Does this completely replace your previous series of 7 patches ? (IE.
> > Should I ditch them in patchwork ?) Or does it apply on top of them ?
>
> It replaces them.
>
On Fri, 17 Jun 2011 12:00:50 +1000
Benjamin Herrenschmidt wrote:
> Does this completely replace your previous series of 7 patches ? (IE.
> Should I ditch them in patchwork ?) Or does it apply on top of them ?
It replaces them.
> > #define SET_IVOR(vector_number, vector_offset) \
> > diff -
On Fri, 2011-06-03 at 17:12 -0500, Scott Wood wrote:
> On MMUs such as FSL where we can guarantee the entire linear mapping is
> bolted, we don't need to worry about linear TLB misses. If on top of
> that we do a full table walk, we get rid of all recursive TLB faults, and
> can dispense with some
On MMUs such as FSL where we can guarantee the entire linear mapping is
bolted, we don't need to worry about linear TLB misses. If on top of
that we do a full table walk, we get rid of all recursive TLB faults, and
can dispense with some state saving. This gains a few percent on
TLB-miss-heavy wo
