On Sat, 18 Jun 2011 08:44:29 +1000 Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote:
> Can't you just re-org the PACA instead ? (with a comment) ? Or at least > if you want to keep it that way, put the cache line explanation in a > comment somewhere. OK. > > > > +.macro tlb_prolog_bolted addr > > > > + mtspr SPRN_SPRG_TLB_SCRATCH,r13 > > > > + mfspr r13,SPRN_SPRG_PACA > > > > + std r10,PACA_EXTLB+EX_TLB_R10(r13) > > > > + mfcr r10 > > > > + std r11,PACA_EXTLB+EX_TLB_R11(r13) > > > > + mfspr r11,SPRN_SPRG_TLB_SCRATCH > > > > > > Do you need that ? Can't you leave r13 in scratch the whole way and > > > just pop it out in the error case when branching to DSI/ISI ? The only > > > thing is that TLB_SCRATCH needs to be saved/restored by > > > crit/debug/mcheck but thats worth saving cycles in the TLB miss handler > > > no ? > > > > Sounds right... I'll try it. This saved another 1% or so. I don't think TLB_SCRATCH needs to be saved by crit/debug/mcheck -- they shouldn't be taking TLB misses, at least in the bolted case. Even non-bolted, it doesn't look like there are enough extlb levels to deal with a linear TLB miss inside a crit/debug/mcheck inside a linear TLB miss inside a virtual page table miss inside a normal TLB miss. Currently, we could just as well take that crit/debug/mcheck after storing to TLB_SCRATCH but before saving it to extlb, and have the same problem. -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
