Re: [PATCH] powerpc/64s: fix scv entry fallback flush vs interrupt

2021-01-24 Thread Michael Ellerman
On Mon, 11 Jan 2021 16:24:08 +1000, Nicholas Piggin wrote: > The L1D flush fallback functions are not recoverable vs interrupts, > yet the scv entry flush runs with MSR[EE]=1. This can result in a > timer (soft-NMI) or MCE or SRESET interrupt hitting here and overwriting > the EXRFI save area, whic

[PATCH] powerpc/64s: fix scv entry fallback flush vs interrupt

2021-01-10 Thread Nicholas Piggin
The L1D flush fallback functions are not recoverable vs interrupts, yet the scv entry flush runs with MSR[EE]=1. This can result in a timer (soft-NMI) or MCE or SRESET interrupt hitting here and overwriting the EXRFI save area, which ends up corrupting userspace registers for scv return. Fix this