On Mon, 11 Jan 2021 16:24:08 +1000, Nicholas Piggin wrote:
> The L1D flush fallback functions are not recoverable vs interrupts,
> yet the scv entry flush runs with MSR[EE]=1. This can result in a
> timer (soft-NMI) or MCE or SRESET interrupt hitting here and overwriting
> the EXRFI save area, which ends up corrupting userspace registers for
> scv return.
>
> Fix this by disabling RI and EE for the scv entry fallback flush.
Applied to powerpc/fixes.
[1/1] powerpc/64s: fix scv entry fallback flush vs interrupt
https://git.kernel.org/powerpc/c/08685be7761d69914f08c3d6211c543a385a5b9c
cheers
