On Tue, 3 Feb 2009, Josh Boyer wrote:
> On Mon, Feb 02, 2009 at 11:24:18AM +1100, Benjamin Herrenschmidt wrote:
> >The PCI 2.x cells used on some 44x SoCs only let us configure the decode
> >for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
> >is a 36-bit bus) are hard wired to
> Could it be my USB failures were due to the PPC440 USB host needing the
> various
> CONFIG*USB*BIG_ENDIAN* options, which may conflict with USB hosts on PCI
> plug-in cards?
>
> The E1000 did work fine.
You need to enable support for both endians, that's supposed to work.
Ben.
On Tue, 3 Feb 2009, Josh Boyer wrote:
> On Mon, Feb 02, 2009 at 11:24:18AM +1100, Benjamin Herrenschmidt wrote:
> >The PCI 2.x cells used on some 44x SoCs only let us configure the decode
> >for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
> >is a 36-bit bus) are hard wired to
On Mon, Feb 02, 2009 at 11:24:18AM +1100, Benjamin Herrenschmidt wrote:
>The PCI 2.x cells used on some 44x SoCs only let us configure the decode
>for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
>is a 36-bit bus) are hard wired to different values depending on the
>specific S
On Mon, 2 Feb 2009, Benjamin Herrenschmidt wrote:
> The PCI 2.x cells used on some 44x SoCs only let us configure the decode
> for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
> is a 36-bit bus) are hard wired to different values depending on the
> specific SoC in use. Our cod
The PCI 2.x cells used on some 44x SoCs only let us configure the decode
for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
is a 36-bit bus) are hard wired to different values depending on the
specific SoC in use. Our code used to work "by accident" until I added
support for the
