David Miller wrote:
From: "Chris Friesen" <[EMAIL PROTECTED]>
Are there any plans for a mechanism to allow the kernel to figure
out (or be told) what packets cpu-affined tasks are interested in
and route the interrupts appropriately?
No, not at all.
Now there are plans to allow the user t
On Oct 27, 2008, at 2:49 PM, David Miller wrote:
From: Kumar Gala <[EMAIL PROTECTED]>
Date: Mon, 27 Oct 2008 14:43:29 -0500
I haven't been following the netdev patches, but what about HW that
does flow separation w/o multiple interrupts?
We (Freescale) are working on such a device:
http:/
On Oct 27, 2008, at 3:27 PM, Benjamin Herrenschmidt wrote:
On Mon, 2008-10-27 at 08:43 -0500, Kumar Gala wrote:
While we have the comment the code appears not to really follow it.
We appear to write 1 << hard_smp_processor_id().
That code is called by each CPU that gets onlined and OR's it'
On Mon, 2008-10-27 at 08:43 -0500, Kumar Gala wrote:
>
> While we have the comment the code appears not to really follow it.
> We appear to write 1 << hard_smp_processor_id().
That code is called by each CPU that gets onlined and OR's it's
bit in the mask.
Ben.
_
From: Kumar Gala <[EMAIL PROTECTED]>
Date: Mon, 27 Oct 2008 14:43:29 -0500
> I haven't been following the netdev patches, but what about HW that does flow
> separation w/o multiple interrupts?
>
> We (Freescale) are working on such a device:
>
> http://www.freescale.com/webapp/sps/site/prod_sum
On Oct 27, 2008, at 1:28 PM, David Miller wrote:
From: "Chris Friesen" <[EMAIL PROTECTED]>
Date: Mon, 27 Oct 2008 11:36:21 -0600
David Miller wrote:
From: Kevin Diggs <[EMAIL PROTECTED]>
Date: Sat, 25 Oct 2008 15:53:46 -0700
What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
From: "Chris Friesen" <[EMAIL PROTECTED]>
Date: Mon, 27 Oct 2008 13:10:55 -0600
> David Miller wrote:
> > From: "Chris Friesen" <[EMAIL PROTECTED]>
>
> > Hello, we either have hardware that does flow seperation and has multiple
> > RX queues going to multiple MSI-X interrupts or we do flow sepera
David Miller wrote:
From: "Chris Friesen" <[EMAIL PROTECTED]>
What about something like the Cavium Octeon, where we have 16 cores but a
single core isn't powerful enough to keep up with a gigE device?
Hello, we either have hardware that does flow seperation and has multiple
RX queues going t
From: "Chris Friesen" <[EMAIL PROTECTED]>
Date: Mon, 27 Oct 2008 11:36:21 -0600
> David Miller wrote:
> > From: Kevin Diggs <[EMAIL PROTECTED]>
> > Date: Sat, 25 Oct 2008 15:53:46 -0700
> >
> >> What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
> >> thing supposed to be able to spr
David Miller wrote:
From: Kevin Diggs <[EMAIL PROTECTED]>
Date: Sat, 25 Oct 2008 15:53:46 -0700
What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
thing supposed to be able to spread irq between its cpus?
Networking interrupts should lock onto a single CPU, unconditionally.
That
On Oct 26, 2008, at 1:33 AM, Benjamin Herrenschmidt wrote:
On Sat, 2008-10-25 at 21:04 -0700, David Miller wrote:
But back to my original wonder, since I've always tipped off of this
generic IRQ layer cpu mask, when was it ever defaulting to zero
and causing the behvaior your powerpc guys actu
On Sun, 2008-10-26 at 18:30 -0800, Kevin Diggs wrote:
> The reason I asked is that I seem to remember a config option that
> would restrict the irqs to cpu 0? Help suggested it was needed for
> certain PowerMacs. Didn't provide any help as to which ones. My GigE
> currently spreads them between the
Benjamin Herrenschmidt wrote:
What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
thing supposed to be able to spread irq between its cpus?
Depends on the interrupt controller. I don't know that machine
but for example the Apple Dual G5's use an MPIC that can spread
based on an in
On Sun, 2008-10-26 at 00:16 -0700, David Miller wrote:
> From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
> Date: Sun, 26 Oct 2008 17:48:43 +1100
>
> >
> > > What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
> > > thing supposed to be able to spread irq between its cpus?
> >
> > D
From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Sun, 26 Oct 2008 17:48:43 +1100
>
> > What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
> > thing supposed to be able to spread irq between its cpus?
>
> Depends on the interrupt controller. I don't know that machine
> but for
> What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
> thing supposed to be able to spread irq between its cpus?
Depends on the interrupt controller. I don't know that machine
but for example the Apple Dual G5's use an MPIC that can spread
based on an internal HW round robin scheme.
On Sat, 2008-10-25 at 21:04 -0700, David Miller wrote:
> But back to my original wonder, since I've always tipped off of this
> generic IRQ layer cpu mask, when was it ever defaulting to zero
> and causing the behvaior your powerpc guys actually want? :-)
Well, I'm not sure what Kumar wants. Most
From: Kevin Diggs <[EMAIL PROTECTED]>
Date: Sat, 25 Oct 2008 15:53:46 -0700
> What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
> thing supposed to be able to spread irq between its cpus?
Networking interrupts should lock onto a single CPU, unconditionally.
That's the optimal way t
From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Sun, 26 Oct 2008 08:33:09 +1100
> Well, I don't know how you do it but on powerpc, we explicitely fill the
> affinity masks at boot time when we can spread interrupts... Maybe we
> should change it the other way around and limit the mask when
Benjamin Herrenschmidt wrote:
On Fri, 2008-10-24 at 16:18 -0700, David Miller wrote:
From: Kumar Gala <[EMAIL PROTECTED]>
Date: Fri, 24 Oct 2008 10:57:38 -0500
Commit 18404756765c713a0be4eb1082920c04822ce588 introduced a regression
on a subset of SMP based PPC systems whose interrupt control
On Fri, 2008-10-24 at 16:18 -0700, David Miller wrote:
> From: Kumar Gala <[EMAIL PROTECTED]>
> Date: Fri, 24 Oct 2008 10:57:38 -0500
>
> > Commit 18404756765c713a0be4eb1082920c04822ce588 introduced a regression
> > on a subset of SMP based PPC systems whose interrupt controller only
> > allow set
From: Kumar Gala <[EMAIL PROTECTED]>
Date: Fri, 24 Oct 2008 10:57:38 -0500
> Commit 18404756765c713a0be4eb1082920c04822ce588 introduced a regression
> on a subset of SMP based PPC systems whose interrupt controller only
> allow setting an irq to a single processor. The previous behavior
> was onl
Commit 18404756765c713a0be4eb1082920c04822ce588 introduced a regression
on a subset of SMP based PPC systems whose interrupt controller only
allow setting an irq to a single processor. The previous behavior
was only CPU0 was initially setup to get interrupts. Revert back
to that behavior.
Signed
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