On 03/25/2014 10:17 AM, 许久成 wrote:
Hi All,
We run into an issue when use e500mc toolchain g++ to compile c++
code for p2020 platform, the code as below:
Hmm, p2020 should be e500 core rather than e500mc. Additionally, you
should use gdb to debug it, and check which instruction is illegal.
On 01/07/2014 02:35 PM, Scott Wood wrote:
On Tue, 2014-01-07 at 09:00 +0800, wyang wrote:
Yeah, Can you provide more detail info about why they can handle that
case? The following is my understand:
Let us assume that there is a atomic global variable(var_a) and its
initial value is 0.
The
On 01/07/2014 06:05 AM, Scott Wood wrote:
On Mon, 2014-01-06 at 13:27 +0800, wyang wrote:
On 01/06/2014 11:41 AM, Gavin Hu wrote:
Thanks your response. :)
But that means that these optimitive operations like atomic_add()
aren't optimitive actully in PPC architecture, right? Becuase the
On 01/06/2014 02:24 PM, Gavin Hu wrote:
So, these primitive funcitons like atomic_add() and so on also can't
prevent processes schedule switch on local CPU core? right?
You are right!
BR
Wei
Thanks!
BR
Gvain. Hu
On Mon, Jan 6, 2014 at 1:27 PM, wyang <mailto:w90p...@gmail.com
;counter)
: "r" (a), "r" (&v->counter)
: "cc");
}
BR
Gavin. Hu
On Mon, Dec 30, 2013 at 9:54 AM, wyang <mailto:w90p...@gmail.com>> wrote:
On 12/28/2013 01:41 PM, Gavin Hu wrote:
Hi
I notice that there is a pair ppc instructions l
On 12/28/2013 01:41 PM, Gavin Hu wrote:
Hi
I notice that there is a pair ppc instructions lwarx and stwcx used to
atomtic operation for instance, atomic_inc/atomic_dec.
In some ppc manuals, they more emphasize its mechanism is that lwarx
can reseve the target memory address preventing other
On 12/26/2013 01:09 PM, Ashish Khetan wrote:
Hi,
I was trying to port Linux-3.12 for MPC8641 based custom designed
board for evaluation purpose. I have been facing a kernel bug at mpic
initialization. Is somebody have faced this kind of bugs or can give
me any pointer for further steps how to
