t; array, 2, 4);
> + sz = (sz == -EINVAL) ? 0 : sz; /* Missing property is OK */
> + if (sz < 0)
> + return dev_err_probe(&client->dev, sz, "invalid
> pll-reset-mode");
Needs a newline on the printk message.
> + if (sz % 2)
> + return dev_err_probe(&client->dev, -EINVAL,
> +"missing pll-reset-mode for pll %d\n",
> array[sz - 1]);
> +
With those fixed
Acked-by: Stephen Boyd # clk
Quoting Sean Anderson (2022-12-29 16:01:33)
> This adds support for the PLLs found in Lynx 10G "SerDes" devices found on
> various NXP QorIQ SoCs. There are two PLLs in each SerDes. This driver has
> been split from the main PHY driver to allow for better review, even though
> these PLLs are not pr
Quoting Peter Zijlstra (2023-01-12 11:43:55)
> OMAP was the one and only user.
>
> Signed-off-by: Peter Zijlstra (Intel)
> Reviewed-by: Ulf Hansson
> Acked-by: Rafael J. Wysocki
> Acked-by: Frederic Weisbecker
> Tested-by: Tony Lindgren
> Tested-by: Ulf Hansson
> ---
Acked-by: Stephen Boyd
Quoting Sean Anderson (2022-12-08 07:36:45)
> On 12/6/22 21:17, Stephen Boyd wrote:
> > Quoting Sean Anderson (2022-11-01 16:27:21)
> >> On 11/1/22 16:10, Stephen Boyd wrote:
> >> >>
> >> >> Oh, I remember why I did this. I need the reference clock
Quoting Sean Anderson (2022-11-01 16:27:21)
> On 11/1/22 16:10, Stephen Boyd wrote:
> >>
> >> Oh, I remember why I did this. I need the reference clock for
> >> clk_hw_round_rate,
> >> which is AFAICT the only correct way to implement round_rate.
> >&
Quoting Sean Anderson (2022-10-28 09:33:59)
> On 10/28/22 12:13, Sean Anderson wrote:
> > On 10/27/22 19:03, Stephen Boyd wrote:
> >>> + ref = devm_clk_get(dev, ref_name);
> >>> + if (IS_ERR(clk->ref)) {
> >>> + ret = PTR_ER
Quoting Sean Anderson (2022-10-28 09:13:57)
> On 10/27/22 19:03, Stephen Boyd wrote:
> > Quoting Sean Anderson (2022-10-27 12:11:08)
> >> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> >> index 853958fb2c06..a6f9e39b 100644
> >>
Quoting Sean Anderson (2022-10-27 12:11:08)
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index 853958fb2c06..a6f9e39b 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -47,3 +47,25 @@ config PHY_FSL_LYNX_28G
> fou
These are for use only in the device tree, and are not
> otherwise used by the driver.
>
> Signed-off-by: Sean Anderson
> Acked-by: Rob Herring
> ---
Acked-by: Stephen Boyd
These are for use only in the device tree, and are not
> otherwise used by the driver.
>
> Signed-off-by: Sean Anderson
> Acked-by: Rob Herring
> ---
Acked-by: Stephen Boyd
Quoting Peter Zijlstra (2022-09-19 03:00:18)
> OMAP was the one and only user.
>
> Signed-off-by: Peter Zijlstra (Intel)
> ---
Acked-by: Stephen Boyd
These are for use only in the device tree, and are not
> otherwise used by the driver.
>
> Signed-off-by: Sean Anderson
> Acked-by: Rob Herring
> ---
Acked-by: Stephen Boyd
Quoting Peter Zijlstra (2022-06-08 07:27:59)
> OMAP was the one and only user.
>
> Signed-off-by: Peter Zijlstra (Intel)
> ---
Acked-by: Stephen Boyd
asmus Villemoes
> Signed-off-by: Andrew Morton
> ---
> drivers/clk/analogbits/wrpll-cln28hpc.c | 4 +
Acked-by: Stephen Boyd
Quoting Geert Uytterhoeven (2020-11-30 00:57:43)
> The R9A06G032 clock driver uses an array of packed structures to reduce
> kernel size. However, this array contains pointers, which are no longer
> aligned naturally, and cannot be relocated on PPC64. Hence when
> compile-testing this driver on P
packed accesses, the
> net size increase is only 76 bytes (gcc 9.3.0 on arm32).
>
> Reported-by: Stephen Rothwell
> Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver")
> Signed-off-by: Geert Uytterhoeven
> ---
Acked-by: Stephen Boyd
Unless you want me to pick this up for clk-fixes?
Quoting Mian Yousaf Kaukab (2020-04-21 01:30:00)
> Add a platform device for qoirq-cpufreq driver for the compatible
> clockgen blocks.
>
> Reviewed-by: Yuantian Tang
> Acked-by: Viresh Kumar
> Signed-off-by: Mian Yousaf Kaukab
> ---
Acked-by: Stephen Boyd
Quoting Mauro Carvalho Chehab (2020-02-22 01:00:03)
> Several references got broken due to txt to ReST conversion.
>
> Several of them can be automatically fixed with:
>
> scripts/documentation-file-ref-check --fix
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
> drivers/hwtracing/core
Quoting Geert Uytterhoeven (2020-02-12 02:17:36)
> The PowerPC time code is not a clock provider, and just needs to call
> of_clk_init().
>
> Hence it can include instead of .
>
> Signed-off-by: Geert Uytterhoeven
> ---
Reviewed-by: Stephen Boyd
This has an ifdef a
Quoting Jonas Gorski (2019-04-23 03:39:59)
> No purpose at all, it's an uncaught artifact from rebasing ._.
>
> Stephen, which one is your preferred way of fixing that?
>
> a) a new V4 patchset without this line
> b) a follow up patch that removes it
> c) just removing the line yourself
I'll go
Quoting Jonas Gorski (2019-04-18 04:12:11)
> Now that clk_{readl,writel} is just an alias for {readl,writel}, we can
> switch all users of clk_* to use the accessors directly and remove the
> helpers.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-18 04:12:10)
> Now that the powerpc clocks are properly marked as big endian, we can
> remove the special handling for PowerPC.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-18 04:12:09)
> These clocks' registers are accessed as big endian, so mark them as
> such.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-18 04:12:08)
> Add a clock specific flag to switch register accesses to big endian, to
> allow runtime configuration of big endian mux clocks.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-18 04:12:07)
> Add a clock specific flag to switch register accesses to big endian, to
> allow runtime configuration of big endian multiplier clocks.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-18 04:12:06)
> Add a clock specific flag to switch register accesses to big endian, to
> allow runtime configuration of big endian gated clocks.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-18 04:12:05)
> Add a clock specific flag to switch register accesses to big endian, to
> allow runtime configuration of big endian fractional divider clocks.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-18 04:12:04)
> Add a clock specific flag to switch register accesses to big endian, to
> allow runtime configuration of big endian divider clocks.
>
> Signed-off-by: Jonas Gorski
> ---
Applied to clk-next
Quoting Jonas Gorski (2019-04-15 03:10:39)
> @@ -370,7 +388,7 @@ static long clk_divider_round_rate(struct clk_hw *hw,
> unsigned long rate,
> if (divider->flags & CLK_DIVIDER_READ_ONLY) {
> u32 val;
>
> - val = clk_readl(divider->reg) >> divider->shift;
> +
Quoting Jonas Gorski (2019-04-15 03:10:40)
> diff --git a/drivers/clk/clk-fractional-divider.c
> b/drivers/clk/clk-fractional-divider.c
> index fdfe2e423d15..b9988d3b3828 100644
> --- a/drivers/clk/clk-fractional-divider.c
> +++ b/drivers/clk/clk-fractional-divider.c
> @@ -13,6 +13,22 @@
> #inclu
Quoting Jonas Gorski (2019-04-08 03:20:34)
> Add a generic flag to mark a clock as big endian register based, and add
> accessors following these.
I like the idea of getting rid of clk_readl() and clk_writel(), but I'd
rather see that this flag is per-basic clk type instead of global to all
clks.
Quoting Vabhav Sharma (2019-02-26 02:10:46)
> These patches were reviewed and acked but dropped during merge window.
> Patchwork link was https://lore.kernel.org/patchwork/cover/1004155/
>
> Changes for v1:
> - Updated lx2160a clockgen in alphabetical order
>
> Vabhav Sharma (2):
> dt-bindings:
Quoting Yuantian Tang (2018-10-30 23:57:36)
> Add more SoC compatible strings to support more chips.
>
> Signed-off-by: Yuantian Tang
> ---
Acked-by: Stephen Boyd
Quoting Vabhav Sharma (2018-10-14 10:08:00)
> From: Yogesh Gaur
>
> Increase size of cmux_to_group array, to accomdate entry of
> -1 termination.
>
> Added -1, terminated, entry for 4080_cmux_grpX.
>
> Signed-off-by: Yogesh Gaur
> Signed-off-by: Vabhav Sharma
> ---
Acked-by: Stephen Boyd
Quoting Vabhav Sharma (2018-10-14 19:58:15)
> > > +
> > > + pmu {
> > > + compatible = "arm,cortex-a72-pmu";
> > > + interrupts = ;
> > > + };
> > > +
> > > + psci {
> > > + compatible = "arm,psci-0.2";
> > > + method = "smc";
> > > + };
> > > +
> > >
Same subject comment.
Quoting Vabhav Sharma (2018-09-23 17:08:59)
> From: Yogesh Gaur
>
> Add clockgen support for lx2160a.
Subject should be "clk: qoriq: increase array size ..."
gesh Gaur
> Signed-off-by: Vabhav Sharma
> ---
Acked-by: Stephen Boyd
On 06/20, frowand.l...@gmail.com wrote:
> From: Frank Rowand
>
> __of_attach_node() is not used outside of drivers/of/dynamic.c. Make
> it static and remove it from drivers/of/of_private.h.
>
> Signed-off-by: Frank Rowand
> ---
Reviewed-by: Stephen Boyd
--
Qualcomm I
On 04/19, Stephen Boyd wrote:
> This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate
> CLK_IS_ROOT", 2016-02-02) so remove it.
>
> Cc: Gerhard Sittig
> Signed-off-by: Stephen Boyd
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a me
This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate
CLK_IS_ROOT", 2016-02-02) so remove it.
Cc: Gerhard Sittig
Signed-off-by: Stephen Boyd
---
arch/powerpc/platforms/512x/clock-commonclk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc
On 03/31/2016 08:07 PM, Yangbo Lu wrote:
> drivers/clk/clk-qoriq.c | 3 +--
>
For clk part:
Acked-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative P
On 01/12, Lothar Waßmann wrote:
> This patchset adds the clock which is necessary to operate the KPP
> unit on i.MX6UL.
> The first patch removes bogus whitespace before TABs in indentation.
> The second patch adds the clock definition.
>
Both look fine. Shawn?
--
Qualcomm Innovation Center, In
(including a workaround for
> old ls1021a device trees that are missing compatible and reg in the
> clockgen node, which even the old binding required). The pll/mux
> details in old device trees will be ignored, but "clocks" properties
> pointing at the old nodes will still work
On 09/19, Scott Wood wrote:
> LS2080A is the first implementation of the chassis 3 clockgen, which
> has a different register layout than previous chips. It is also little
> endian, unlike previous chips.
>
> Signed-off-by: Scott Wood
> ---
Acked-by: Stephen Boyd
--
Q
On 06/18/2015 08:30 AM, Guenter Roeck wrote:
> On Wed, Jun 17, 2015 at 06:04:54PM -0700, Stephen Boyd wrote:
> [ ... ]
>> What happened to this series? I want to add shutdown support to my
>> platform and I need to write a register on the PMIC in one driver to
>> configure
On 10/06/2014 10:28 PM, Guenter Roeck wrote:
> Various drivers implement architecture and/or device specific means to
> remove power from the system. For the most part, those drivers set the
> global variable pm_power_off to point to a function within the driver.
>
> This mechanism has a number of
On 05/06, Scott Wood wrote:
> On Wed, 2015-05-06 at 00:02 -0700, Stephen Boyd wrote:
> > On 04/16, Igal.Liberman wrote:
> > > +static int get_fm_clk_idx(int fm_id, int *fm_clk_idx)
> > > +{
> > > + struct ccsr_guts __iomem *guts_regs = NULL;
> >
&g
On 04/16, Igal.Liberman wrote:
> From: Igal Liberman
>
> This patch depends on the following patches:
> https://patchwork.ozlabs.org/patch/461151/
> https://patchwork.ozlabs.org/patch/461155/
>
> This patche is described by the following binding document update:
> https://patch
well defined and widely used.
>
> Signed-off-by: Sudeep Holla
> Cc: Greg Kroah-Hartman
> Cc: Stephen Boyd
> Cc: linux-...@vger.kernel.org
> Cc: linux...@de.ibm.com
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-i...@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.o
nux-mips.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux...@vger.kernel.org
Cc: sparcli...@vger.kernel.org
Cc: Chris Metcalf
Cc: user-mode-linux-de...@lists.sourceforge.net
Cc: x...@kernel.org
Signed-off-by: Stephen Boyd
---
This is on top of mmotm's lib-conslidate-debug_per_cpu_ma
: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Stephen Boyd
---
I don't know what tree to send this through, so I'm sending it to
Andrew. I suppose mm is as good as anything.
arch/powerpc/Kconfig.debug | 12
arch/x86/Kconfig.debug | 11 ---
lib/Kconfig.debug
On 01/14/2011 11:19 AM, Tony Lindgren wrote:
> * Stephen Boyd [101207 11:00]:
>> On 12/01/2010 12:20 PM, Stephen Boyd wrote:
>>> Definitely for TX since it seems like a redundant loop, but I agree RX
>>> code has changed. Instead of
>>>
>>> If RX buf
On 12/01/2010 12:20 PM, Stephen Boyd wrote:
> Definitely for TX since it seems like a redundant loop, but I agree RX
> code has changed. Instead of
>
> If RX buffer full
> Poll for RX buffer full
> Read character from RX buffer
>
> we would have
>
> If RX buffer
On 12/01/2010 10:54 AM, Daniel Walker wrote:
> Are you talking about __dcc_getstatus only? I don't think adding
> volatile is going to hurt anything, if not having it causes problems.
>
Just marking __dcc_getstatus volatile gives me
0038 :
38: ee10fe11mrc 14, 0, pc, cr0, cr1,
On 11/30/2010 11:25 AM, Daniel Walker wrote:
> @@ -682,6 +682,15 @@ config HVC_UDBG
> select HVC_DRIVER
> default n
>
> +config HVC_DCC
> + bool "ARM JTAG DCC console"
> + depends on ARM
> + select HVC_DRIVER
> + help
> + This console uses the JTAG
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