Fix i8259 kernel crash on ML510

>From 11a2072b285c2eb0f19980ad729229d4ebf22291 Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Thu, 3 Sep 2009 15:11:08 +0200 Subject: [PATCH] This patch fixes a null pointer exception caused by removal of 'ack()' for level interrupts in the Xilinx interrupt driver. ---

Fix i8259 kernel crash on ML510 [with signed-off]

Hi, This is the same patch but with a signed-off message which I forgot. Regards, Roderick Colenbrander Signed-off-by: Roderick Colenbrander >From 11a2072b285c2eb0f19980ad729229d4ebf22291 Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Thu, 3 Sep 2009 15:11:08 +0200 Subj

Re: PowerPC PCI DMA issues (prefetch/coherency?)

e outgoing window 0x-0x9fff or just set it half way at 0x8000. I'm not saying this is your issue but it could be it. Regards, Roderick Colenbrander On Tue, Jun 16, 2009 at 4:08 PM, Chris Pringle wrote: > Hello All > > We're developing on a Freescale MPC8272 a

Re: [PATCH v5 0/4] Series short description

On Tue, May 26, 2009 at 2:41 PM, Roderick Colenbrander wrote: > On Mon, May 25, 2009 at 10:47 PM, Roderick Colenbrander > wrote: >> On Mon, May 25, 2009 at 4:41 PM, Grant Likely >> wrote: >>> Repost of ml510 series.  This time against 2.6.30-rc7 and with the .dts &

Re: [PATCH v5 0/4] Series short description

On Mon, May 25, 2009 at 10:47 PM, Roderick Colenbrander wrote: > On Mon, May 25, 2009 at 4:41 PM, Grant Likely > wrote: >> Repost of ml510 series.  This time against 2.6.30-rc7 and with the .dts >> file included. >> >> g. >> >> -- >> Grant Lik

Re: [PATCH v5 0/4] Series short description

On Mon, May 25, 2009 at 4:41 PM, Grant Likely wrote: > Repost of ml510 series.  This time against 2.6.30-rc7 and with the .dts > file included. > > g. > > -- > Grant Likely, B.Sc. P.Eng. > Secret Lab Technologies Ltd. > Thanks, I will check it out tomorrow. Roderick _

Re: [PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference designsupport

Hi Stephen, Grant forgot to attach the dts file (but a next patch will add it). The dts file contains some lines for the pci bus mapping. The lines are attached below. For pci support I'm using the reference bsb with pci 'ML510 BSB1 Pcores Design' for PowerPC at: http://www.xilinx.com/products/boa

Re: [PATCH v4 0/3] Add support for ML510 board

On Thu, May 21, 2009 at 6:24 PM, Grant Likely wrote: > Heck, I don't know if this stuff even works, but I've refactored > Roderick's patches into something closer to the structure that I'd like > to see.  There are still a few things that bother me, but I think it > is mostly there. > > It at leas

Re: [PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference designsupport

> Yeow... I agree about the dirty hack part... shouldn't this be in the > device tree somewhere, or in the ali driver? > > I'm curious if this works on ml410 as well.. (Yes, I know, does this > really matter much? But there are still a bunch of them floating around > in universities.) It may be

Fwd: Patch 2/2: Add Xilinx ML510 reference design support [attempt2]

Hi, As requested here the same patch but now with a signed-off line which I forgot. Regards, Roderick Colenbrander Signed-off-by: Roderick Colenbrander >From f46fa90e4d066767cc4fc1c5b8dc2f9ee013ea0a Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Tue, 14 Apr 2009 15:49:32 +0

Patch 1/2: Add support for Xilinx PLB PCI soft-core [attempt3]

Hi, As requested here the same patch but now with a signed-off line which I forgot. Regards, Roderick Colenbrander Signed-off-by: Roderick Colenbrander >From 2b34a315b18834448c0a8218d4da85ffaf76039e Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Tue, 14 Apr 2009 15:45:07 +0

Re: PowerPC iotable_init equivalent?

*). In general you use an of_* function to look up your periperhal in the device tree. Once you have its node you would able to do e.g. of_iomap (which uses ioremap with the right offsets behind its back) to map the device. So you don't hard code physical addresses anymore in the code. Re

Re: pci32 code - early_*config*

or you would have to access the address and data bus by hand). In my case I'm using a Xilinx PLB soft-core and if certain options in the configuration header aren't set (which aren't set by default) the soft-core is basically disabled. Cases like this look like valid cases in wh

Re: RFC Patch: Use x86 init_hwif in the alim15x3 for x86-like PowerPC systems

On Fri, Apr 17, 2009 at 12:04 AM, Anton Vorontsov wrote: > On Thu, Apr 16, 2009 at 11:27:34PM +0200, Roderick Colenbrander wrote: >> On Thu, Apr 16, 2009 at 10:57 PM, Anton Vorontsov >> wrote: >> > On Thu, Apr 16, 2009 at 09:30:00PM +0200, Bartlomiej Zolnierkiewi

Re: RFC Patch: Use x86 init_hwif in the alim15x3 for x86-like PowerPC systems

On Thu, Apr 16, 2009 at 10:57 PM, Anton Vorontsov wrote: > On Thu, Apr 16, 2009 at 09:30:00PM +0200, Bartlomiej Zolnierkiewicz wrote: >> >> Hi, >> >> On Wednesday 15 April 2009 16:34:22 Roderick Colenbrander wrote: >> > Hi, >> > >> > I'm

Re: OF PCI howto?

value is normally translated using 'xlate' to linux kernel values (active low is defined as IRQ_TYPE_LEVEL_LOW 0x0008 in the kernel). The ipic driver code and various dts files are evil and store the linux kernel value inside the DTS file, so they don't do any conversion whis is EVIL in my opinion. Watch out for that. (The corresponding DTS files and drivers should be updated). Regards, Roderick Colenbrander ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev

Re: Looking for good supported South bridge for mpc6841d

On Wed, Apr 15, 2009 at 1:23 PM, Zhivko Yordanov wrote: > Hello, > > I'm on designing of a new embedded board, based on mpc6841d and South Bridge > ULi M1575. As а reference design, I use Freescale HPCN board. However after > consult with chip's distributor, it became clear that the M1575 is alrea

Patch 2/2: Add Xilinx ML510 reference design support [attempt2]

Hi, This is an updated version of my patch from yesterday it contains some fixes. I had some c++ style comments left in my previous version of this patch and there was a small error in the dts file. Regards, Roderick Colenbrander >From 018041061bc233c09340eff20fcd4e8bc75da1d3 Mon Sep 17 00

Patch 1/2: Add support for Xilinx PLB PCI soft-core [attempt2]

Hi, This is an updated version of the patch which takes into account a few changes suggested by Grant which I forgot to add. Regards, Roderick Colenbrander >From 2b34a315b18834448c0a8218d4da85ffaf76039e Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Tue, 14 Apr 2009 15:45:07 +0

Patch 2/2: Add Xilinx ML510 reference design support

>From f46fa90e4d066767cc4fc1c5b8dc2f9ee013ea0a Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Tue, 14 Apr 2009 15:49:32 +0200 Subject: [PATCH] Add Xilinx ML510 reference design support. --- arch/powerpc/boot/dts/virtex440-ml510.dts | 453 + arch/powe

Patch 1/2: Add support for Xilinx PLB PCI soft-core

>From c1cf80d7e5332240c2e54500476027c23b496b92 Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Tue, 14 Apr 2009 15:45:07 +0200 Subject: [PATCH] Add support for the Xilinx PLB PCI soft-core which is used on Xilinx ML410 and ML510 FPGA boards. --- arch/powerpc/sysdev/Kcon

Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)

the registers above 4GiB, so is common with > almost all the I/O on the other 440 boards? > > The driver works fine on 440 based Xilinx boards (the ML510 I use has a 440 core). It might be nice to move physical addresses above 4GB for devices but in all Xilinx tools and reference designs addresses below 4GB are used for periperhals and I think even below 2GB (or even below 1GB). It depends on the design. Roderick Colenbrander ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev

Draft version of ML510 Linux patch (patch inlined)

Hi, As requested by Grant Likely here the same patch but now inlined. Regards, Roderick Colenbrander diff -urN -X linux-2.6.29/Documentation/dontdiff linux-2.6.29/arch/powerpc/boot/dts/virtex440-ml510.dts ml510-dev/linux-2.6.29/arch/powerpc/boot/dts/virtex440-ml510.dts --- linux-2.6.29/arch

RFC ML510 Linux support

is some ide hack in which I need to submit to the ide list and I guess that I need to make my pci driver OF aware. Regards, Roderick Colenbrander -- Neu: GMX FreeDSL Komplettanschluss mit DSL 6.000 Flatrate + Telefonanschluss für nur 17,95 Euro/mtl.!* http://dsl.gmx.de/?ac

Re: DTS file PCI / i8259 for Xilinx ML510

Original-Nachricht > Datum: Mon, 16 Mar 2009 09:18:54 +0100 > Von: "Roderick Colenbrander" > An: "Gerhard Pircher" , linuxppc-dev@ozlabs.org > Betreff: Re: DTS file PCI / i8259 for Xilinx ML510 > > Original-Nachricht ---

Re: DTS file PCI / i8259 for Xilinx ML510

Original-Nachricht > Datum: Sun, 15 Mar 2009 11:43:13 +0100 > Von: "Gerhard Pircher" > An: "Roderick Colenbrander" , linuxppc-dev@ozlabs.org > Betreff: Re: DTS file PCI / i8259 for Xilinx ML510 > > Original-Nachricht ---

Re: DTS file PCI / i8259 for Xilinx ML510

per DTS file prevent this issue? If not where is the remapping done (I didn't see it). For that reason I'm ignoring the pci-to-pci bridge for now. Thanks, Roderick Colenbrander -- Pt! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimes

Re: DTS file PCI / i8259 for Xilinx ML510

ot sure what the proper layout would be for this in the dts file though. With those changes I mentioned to i8259.c I got some PCI devices of my ali m1553 south bridge working. The code is ugly and I need to do cleanups. When it is done I will submit some patches. Regards, Roderick Colenbrander

DTS file PCI / i8259 for Xilinx ML510

#interrupt-cells = <2>; compatible = "chrp,iic"; interrupts = <9 2>; interrupt-parent = <&mpic>;

DTS file PCI / i8259 for Xilinx ML510

#interrupt-cells = <2>; compatible = "chrp,iic"; interrupts = <9 2>; interrupt-parent = <&mpic>;