On Tue, Feb 08, 2022 at 02:17:03PM +0100, Frederic Weisbecker wrote:
> On Tue, Feb 08, 2022 at 08:32:37AM +0100, Paul Menzel wrote:
> > once warned about a NOHZ tick-stop error, when I executed `sudo
> > /usr/sbin/ppc64_cpu --smt=off` (so that KVM would work).
>
> I see, so I assume this sets some
On Mon, Nov 08, 2021 at 11:30:10AM +0530, Kajol Jain wrote:
> Add pmu metric json file for power10 platform.
>
> Signed-off-by: Kajol Jain
> ---
> Changelog
> v2 -> v3:
> - Did nit changes in BriefDescription as suggested
> by Paul A. Clarke and Michael Ellermen
On Mon, Oct 25, 2021 at 02:23:15PM +1100, Michael Ellerman wrote:
> "Paul A. Clarke" writes:
> > Thanks for the changes!
> > More nits below (many left over from prior review)...
> >
> > On Fri, Oct 22, 2021 at 11:55:05AM +0530, Kajol Jain wrote:
> >>
riefDescription field
> as suggested by Paul A. Clarke
>
> - Link to the v1 patch: https://lkml.org/lkml/2021/10/6/131
>
> .../arch/powerpc/power10/metrics.json | 676 ++
> 1 file changed, 676 insertions(+)
> create mode 100644 tools/perf/pm
On Wed, Oct 06, 2021 at 12:32:48PM -0500, Paul A. Clarke wrote:
> > +{
> > +"BriefDescription": "Average cycles per instruction when the
> > instruction finishes at dispatch",
>
> I'm not sure what that means.
After doing a bit of
Kajol,
On Wed, Oct 06, 2021 at 01:01:19PM +0530, Kajol Jain wrote:
> Add pmu metric json file for power10 platform.
Thanks for producing this! A few minor corrections, plus a number of
stylistic comments below...
> Signed-off-by: Kajol Jain
> ---
> .../arch/powerpc/power10/metrics.json
On Thu, Jul 08, 2021 at 10:56:57PM +1000, Nicholas Piggin wrote:
> Excerpts from Athira Rajeev's message of July 7, 2021 4:39 pm:
> > From: Athira Rajeev
> >
> > Power10 performance monitoring unit (PMU) driver uses performance
> > monitor counter 5 (PMC5) and performance monitor counter 6 (PMC6)
On Mon, Jun 28, 2021 at 11:53:41AM +0530, Kajol Jain wrote:
> Commit 48a1f565261d ("perf script python: Add more PMU fields
> to event handler dict") added functionality to report fields like
> weight, iregs, uregs etc via perf report.
> That commit predefined buffer size to 512 bytes to print thos
On Mon, Jun 28, 2021 at 11:58:54AM +0530, kajoljain wrote:
>
>
> On 6/25/21 6:51 PM, Paul A. Clarke wrote:
> > On Fri, Jun 25, 2021 at 05:29:48PM +0530, Kajol Jain wrote:
> >> Patch adds 24x7 nest metric events for POWER10.
> >>
> >> Signed-off-by: K
On Fri, Jun 25, 2021 at 05:29:48PM +0530, Kajol Jain wrote:
> Patch adds 24x7 nest metric events for POWER10.
>
> Signed-off-by: Kajol Jain
> ---
> .../arch/powerpc/power10/nest_metrics.json| 491 ++
> 1 file changed, 491 insertions(+)
> create mode 100644
> tools/perf/pmu-
On Tue, May 25, 2021 at 09:42:15AM -0500, Paul A. Clarke wrote:
> On Tue, May 25, 2021 at 12:07:23PM +0530, Kajol Jain wrote:
> > Fixed the eventcode values in the power10 json event files to append
> > "0x" since these are hexadecimal values.
> > Patch al
ll the added EventCodes indeed had '0x', the
number of EventCodes added matched the number removed, and that the
additional text added seemed reasonable. LGTM.
Reviewed-by: Paul A. Clarke
the `BriefDescription` ends with a period or not, and whether
there is an extra space at the end.
Regardless, LGTM.
Tested-by: Paul A. Clarke
Reviewed-by: Paul A. Clarke
PC
Another drive-by review... just some minor nits, below...
On Fri, Feb 26, 2021 at 12:20:24PM +0530, Madhavan Srinivasan wrote:
> Introduce code to support the checking of attr.config* for
> values which are reserved for a given platform.
> Performance Monitoring Unit (PMU) configuration registers
On Wed, Feb 24, 2021 at 07:58:39PM +0530, Madhavan Srinivasan wrote:
> Introduce code to support the checking of attr.config* for
> values which are reserved for a given platform.
> Performance Monitoring Unit (PMU) configuration registers
> have fileds that are reserved and specific values to bit
Just one nit in a comment below...
(and this is not worthy of tags like "reviewed-by" ;-)
On Mon, Sep 21, 2020 at 03:10:04AM -0400, Athira Rajeev wrote:
> PMU counter support functions enforces event constraints for group of
> events to check if all events in a group can be monitored. Incase of
>
On Thu, May 21, 2020 at 11:43:40AM +1000, Alistair Popple wrote:
> Matrix multiple assist (MMA) is a new feature added to ISAv3.1 and
s/Matrix multiple assist/Matrix-Multiply Assist/
> POWER10. Support on powernv can be selected via a firmware CPU device
> tree feature which enables it via a PCR
On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
Conclusion is that this should be "Matrix-Multiply Assist", but then there
are a couple more below...
> POWER10. Support on powernv can be selected via a firmw
On Tue, May 19, 2020 at 10:31:51AM +1000, Alistair Popple wrote:
> POWER10 introduces two new architectural features - ISAv3.1 and matrix
> multiply accumulate (MMA) instructions. Userspace detects the presence
> of these features via two HWCAP bits introduced in this patch. These
> bits have been
On Tue, May 19, 2020 at 10:28:55AM -0500, Segher Boessenkool wrote:
> On Tue, May 19, 2020 at 10:22:40AM -0500, Paul A. Clarke wrote:
> > On Tue, May 19, 2020 at 10:05:56AM -0500, Segher Boessenkool wrote:
> > > On Tue, May 19, 2020 at 09:49:22AM -0500, Paul A. Clarke wrote:
>
On Tue, May 19, 2020 at 10:05:56AM -0500, Segher Boessenkool wrote:
> On Tue, May 19, 2020 at 09:49:22AM -0500, Paul A. Clarke wrote:
> > On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> > > Matrix multiple accumulate (MMA) is a new feature added to ISAv3.
On Tue, May 19, 2020 at 10:31:56AM +1000, Alistair Popple wrote:
> Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
nit: "Matrix-Multiply Accelerator".
PC
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