On Mon, 04 Dec 2023 11:08:25 -0500, Frank Li wrote:
> Add suspend/resume support for ls1043 and ls1021.
>
> Change log see each patch
>
> Frank Li (4):
> PCI: layerscape: Add function pointer for exit_from_l2()
> PCI: layerscape: Add suspend/resume for ls1021a
> PCI: layerscape(ep): Rename
On Mon, Oct 16, 2023 at 12:11:04PM -0400, Frank Li wrote:
> On Mon, Oct 16, 2023 at 10:22:11AM -0500, Bjorn Helgaas wrote:
> > On Mon, Oct 16, 2023 at 10:45:25AM -0400, Frank Li wrote:
> > > On Tue, Oct 10, 2023 at 06:02:36PM +0200, Lorenzo Pieralisi wrote:
> > > >
On Mon, Oct 16, 2023 at 10:22:11AM -0500, Bjorn Helgaas wrote:
> On Mon, Oct 16, 2023 at 10:45:25AM -0400, Frank Li wrote:
> > On Tue, Oct 10, 2023 at 06:02:36PM +0200, Lorenzo Pieralisi wrote:
> > > On Tue, Oct 10, 2023 at 10:20:12AM -0400, Frank Li wrote:
>
> > >
On Tue, Oct 10, 2023 at 10:20:12AM -0400, Frank Li wrote:
> On Wed, Oct 04, 2023 at 10:23:51AM -0400, Frank Li wrote:
> > On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > > ls1021a add suspend/resume support.
> > >
> > > Signed-off-by: Frank Li
> > > ---
> >
> > ping
> >
> > Frank
On Tue, 26 Sep 2023 10:04:45 -0400, Frank Li wrote:
> Set DMA mask and coherent DMA mask to enable 64-bit addressing.
>
>
Read this:
https://lore.kernel.org/linux-pci/20171026223701.ga25...@bhelgaas-glaptop.roam.corp.google.com
Find the issue with the commit log (that I fixed).
This does not a
On Thu, 20 Jul 2023 09:58:33 -0400, Frank Li wrote:
> Add support to pass Link down notification to Endpoint function driver
> so that the LINK_DOWN event can be processed by the function.
>
>
Applied to controller/layerscape, thanks!
[1/2] PCI: layerscape: Add support for Link down notificatio
On Wed, Aug 16, 2023 at 11:53:16AM -0400, Frank Li wrote:
> On Mon, Jul 31, 2023 at 11:06:31AM -0400, Frank Li wrote:
> > On Thu, Jul 20, 2023 at 09:58:33AM -0400, Frank Li wrote:
> > > Add support to pass Link down notification to Endpoint function driver
> > > so that the LINK_DOWN event can be p
On Mon, 15 May 2023 11:10:49 -0400, Frank Li wrote:
> Layerscape has PME interrupt, which can be used as linkup notifier.
> Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
> when linkup detected.
>
>
Applied to controller/endpoint, thanks!
[1/1] PCI: layerscape: Add the
On Mon, May 15, 2023 at 11:10:49AM -0400, Frank Li wrote:
> Layerscape has PME interrupt, which can be used as linkup notifier.
> Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
> when linkup detected.
>
> Acked-by: Manivannan Sadhasivam
> Signed-off-by: Xiaowei Bao
> Si
On Thu, 09 Feb 2023 10:10:50 -0500, Frank Li wrote:
> Add PCIe EP mode support for ls1028a.
>
>
Applied to controller/layerscape, thanks!
[1/1] PCI: layerscape: Add EP mode support for ls1028a
https://git.kernel.org/pci/pci/c/be567c6cbc08
Thanks,
Lorenzo
On Mon, Jan 09, 2023 at 03:41:31PM +, Frank Li wrote:
> >
> > From: Xiaowei Bao
> >
> > Add PCIe EP mode support for ls1028a.
> >
> > Signed-off-by: Xiaowei Bao
> > Signed-off-by: Hou Zhiqiang
> > ---
> >
> > All other patches were already accepte by maintainer in
> > https://lore.kernel
On Fri, 21 Jan 2022 08:42:21 +, Christophe Leroy wrote:
> Today drivers/pci/controller/pci-xgene.c defines SZ_1T
>
> Move it into linux/sizes.h so that it can be re-used elsewhere.
>
>
Applied to pci/misc, thanks!
[05/14] sizes.h: Add SZ_1T macro
https://git.kernel.org/lpieralisi/p
On Thu, 11 Mar 2021 03:37:45 +, Krzysztof Wilczyński wrote:
> Replace command with a semicolon to correct syntax and to prevent
> potential unspecified behaviour and/or unintended side effects.
>
> Related:
>
> https://lore.kernel.org/linux-pci/20201216131944.14990-1-zhengyongj...@huawei.co
/patch/20210311033745.1547044-1...@linux.com
For the future email exchanges: don't top-post please.
Thanks,
Lorenzo
> Thanks.
> Roy
>
> -Original Message-
> From: Lorenzo Pieralisi
>
> On Sun, Mar 07, 2021 at 07:36:57PM +0100, Krzysztof Wilczyński wrote:
> > Hi,
&g
On Sun, Mar 07, 2021 at 07:36:57PM +0100, Krzysztof Wilczyński wrote:
> Hi,
>
> [...]
> > I would request NXP maintainers to take this patch, rewrite it as
> > Bjorn requested and resend it as fast as possible, this is a very
> > relevant fix.
> [...]
>
> Looking at the state of the pci-layerscap
On Wed, 20 Jan 2021 11:52:46 +0100, Michael Walle wrote:
> fw_devlink will defer the probe until all suppliers are ready. We can't
> use builtin_platform_driver_probe() because it doesn't retry after probe
> deferral. Convert it to builtin_platform_driver().
Applied to pci/dwc, thanks!
[1/1] PCI:
On Wed, Jan 20, 2021 at 11:52:46AM +0100, Michael Walle wrote:
> fw_devlink will defer the probe until all suppliers are ready. We can't
> use builtin_platform_driver_probe() because it doesn't retry after probe
> deferral. Convert it to builtin_platform_driver().
>
> Fixes: e590474768f1 ("driver
On Wed, Jan 20, 2021 at 08:28:36PM +0100, Michael Walle wrote:
> [RESEND, fat-fingered the buttons of my mail client and converted
> all CCs to BCCs :(]
>
> Am 2021-01-20 20:02, schrieb Saravana Kannan:
> > On Wed, Jan 20, 2021 at 6:24 AM Rob Herring wrote:
> > >
> > > On Wed, Jan 20, 2021 at 4:
On Wed, Jan 06, 2021 at 01:07:22PM -0600, Bjorn Helgaas wrote:
> On Wed, Dec 16, 2020 at 09:19:44PM +0800, Zheng Yongjun wrote:
> > Replace a comma between expression statements by a semicolon.
>
> Looks like a good fix, but read this about the changelog title:
>
> https://lore.kernel.org/r/20171
On Sun, 29 Nov 2020 23:07:38 +, Krzysztof Wilczyński wrote:
> Unify ECAM-related constants into a single set of standard constants
> defining memory address shift values for the byte-level address that can
> be used when accessing the PCI Express Configuration Space, and then
> move native PCI
On Sun, Nov 29, 2020 at 11:07:39PM +, Krzysztof Wilczyński wrote:
> Add ECAM-related constants to provide a set of standard constants
> defining memory address shift values to the byte-level address that can
> be used to access the PCI Express Configuration Space, and then move
> native PCI Exp
On Thu, 5 Nov 2020 15:11:43 -0600, Rob Herring wrote:
> Here's another batch of DWC PCI host refactoring. This series primarily
> moves more of the MSI, link up, and resource handling to the core
> code. Beyond a couple of minor fixes, new in this version is runtime
> detection of iATU regions inst
On Tue, Aug 11, 2020 at 05:54:29PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Add the PCIe EP multiple PF support for DWC and Layerscape, and use
> a list to manage the PFs of each PCIe controller; add the doorbell
> MSIX function for DWC; and refactor the Layerscape EP driver due to
> s
On Sat, Mar 14, 2020 at 11:30:27AM +0800, Xiaowei Bao wrote:
> Add the PCIe EP multiple PF support for DWC and Layerscape, add
> the doorbell MSIX function for DWC, use list to manage the PF of
> one PCIe controller, and refactor the Layerscape EP driver due to
> some platforms difference.
>
> Xia
On Tue, Sep 24, 2019 at 10:18:38AM +0800, Xiaowei Bao wrote:
> Add the PCIe EP multiple PF support for DWC and Layerscape, add
> the doorbell MSIX function for DWC, use list to manage the PF of
> one PCIe controller, and refactor the Layerscape EP driver due to
> some platforms difference.
>
> Xia
On Mon, Sep 02, 2019 at 11:43:17AM +0800, Xiaowei Bao wrote:
> Add the PCIe compatible string for LS1028A
Sentences must be terminated with a period.
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Rob Herring
> ---
> v2:
> - No change.
> v3:
> - No change.
> v4:
>
>
> > -Original Message-
> > From: Xiaowei Bao
> > Sent: Wednesday, November 6, 2019 11:36 AM
> > To: Lorenzo Pieralisi
> > Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org;
> > Leo Li ; M.h. Lian ; Mingkai
> > Hu ; Roy Zang ;
On Thu, Aug 29, 2019 at 10:43:18AM +0530, Kishon Vijay Abraham I wrote:
> Gustavo,
>
> On 27/08/19 6:55 PM, Andrew Murray wrote:
> > On Sat, Aug 24, 2019 at 12:08:40AM +, Xiaowei Bao wrote:
> >>
> >>
> >>> -Original Message-
> >>> From: Andrew Murray
> >>> Sent: 2019年8月23日 21:58
> >>>
On Mon, Sep 02, 2019 at 11:43:19AM +0800, Xiaowei Bao wrote:
> Add support for the LS1028a PCIe controller.
>
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> ---
> v2:
> - No change.
> v3:
> - Reuse the ls2088 driver data structurt.
> v4:
> - No change.
> v5:
> - No change.
> v6
On Fri, Aug 23, 2019 at 04:26:41PM +0800, Xiaowei Bao wrote:
> Add the PCIe compatible string for LS1028A
>
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Rob Herring
> ---
> v2:
> - No change.
> v3:
> - No change.
> v4:
> - No change.
>
> Documentation/devicetre
On Wed, Aug 14, 2019 at 09:48:00AM +, Xiaowei Bao wrote:
>
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: 2019年8月14日 17:30
> > To: Xiaowei Bao
> > Cc: M.h. Lian ; Mingkai Hu
> > ; Roy Zang ;
> > bhelg...@goog
I asked you to remove the period at the end of the patch $SUBJECT and
you did not, either you do not read what I write or explain me what's
going on.
On Wed, Aug 14, 2019 at 10:03:29AM +0800, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR2 an
git log --oneline --follow drivers/pci/controller/dwc/pci-layerscape.c
Do you see any commit with a $SUBJECT ending with a period ?
There is not. So remove it from yours too.
On Tue, Aug 13, 2019 at 02:28:39PM +0800, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 a
You should fix your email client set-up to avoid sticking an [EXT]
tag to your emails $SUBJECT.
On Tue, Aug 13, 2019 at 07:39:48AM +, Xiaowei Bao wrote:
>
>
> > -Original Message-
> > From: Kishon Vijay Abraham I
> > Sent: 2019年8月13日 15:30
> > To: Xiaowei Bao ; lorenzo.pieral...@arm
On Mon, Aug 12, 2019 at 10:39:00AM +, Xiaowei Bao wrote:
>
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: 2019年8月12日 18:12
> > To: Xiaowei Bao ; kis...@ti.com
> > Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
First off:
Trim the CC list, you CC'ed maintainers (and mailing lists) for no
reasons whatsover.
Then, read this:
https://lore.kernel.org/linux-pci/20171026223701.ga25...@bhelgaas-glaptop.roam.corp.google.com/
and make your patches compliant please.
On Fri, Jun 28, 2019 at 09:38:25AM +0800, Xi
On Fri, Jun 28, 2019 at 09:38:26AM +0800, Xiaowei Bao wrote:
> Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately.
>
> Signed-off-by: Xiaowei Bao
> ---
> v2:
> - No change.
> v3:
> - modify the commit message.
>
> drivers/pci/controller/dwc/Kconfig | 20 ++--
> drivers/
ing object release within this function.
> ./drivers/pci/controller/dwc/pci-dra7xx.c:255:1-7: ERROR: missing
> of_node_put; acquired a node pointer with refcount incremented on line 241,
> but without a corresponding object release within this function.
>
> Signed-off-by: Wen Yang
On Wed, Feb 20, 2019 at 03:09:01AM +, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: 2019年2月19日 19:27
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo
On Tue, Jan 22, 2019 at 02:33:27PM +0800, Xiaowei Bao wrote:
> Add the PCIe EP mode support for layerscape platform.
>
> Signed-off-by: Xiaowei Bao
> Reviewed-by: Minghuan Lian
> Reviewed-by: Zhiqiang Hou
> Reviewed-by: Kishon Vijay Abraham I
> ---
> depends on: https://patchwork.kernel.org/pr
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape PCIe
> controller with EP mode.
>
> Signed-off-by: Xiaowei Bao
> Reviewed-by: Minghuan Lian
> Reviewed-by: Zhiqiang Hou
> Reviewed-by: Rob Herring
> ---
> v2:
>
Rob,
Is it OK for you if I pull this series into the pci tree ?
Please let me know, thanks.
Lorenzo
On Mon, Jan 21, 2019 at 05:44:57PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape PCIe
> controller with EP mode.
>
> Signed-off-by: Xiaowei Bao
On Mon, Nov 05, 2018 at 04:46:52PM +0800, Xiaowei Bao wrote:
> Add the PCIe EP mode support for layerscape platform.
>
> Signed-off-by: Xiaowei Bao
> ---
> v2:
> - remove the EP mode check function.
>
> drivers/pci/controller/dwc/Makefile|2 +-
> drivers/pci/controller/dwc/pci-
On Mon, Nov 05, 2018 at 04:46:50PM +0800, Xiaowei Bao wrote:
> Add the EP mode support.
>
> Signed-off-by: Xiaowei Bao
> ---
> v2:
> - Add the SoC specific compatibles.
>
> .../devicetree/bindings/pci/layerscape-pci.txt |3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
Wrong
On Fri, Nov 10, 2017 at 11:48:44AM +0800, Bao Xiaowei wrote:
> Depend on http://patchwork.ozlabs.org/patch/815382/
>
> Bao Xiaowei (3):
> ARMv8: dts: ls1046a: add the property of IB and OB
> ARMv8: layerscape: add the pcie ep function support
> ARMv8: pcie: make the DWC EP driver support for
On Mon, Nov 13, 2017 at 02:35:48AM +, M.h. Lian wrote:
[...]
> > > On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> > > > Add the property of inbound and outbound windows number for ep driver.
> > > >
> > > > Signed-off-by: Bao Xiaowei
> > > > Acked-by: Minghuan Lian
> > > > ---
>
On Thu, Aug 17, 2017 at 09:30:28PM +1000, Daniel Axtens wrote:
> A system without PCI legacy resources (e.g. ARM64) may find that no
> default/boot VGA device has been marked, because the VGA arbiter
> checks for legacy resource decoding before marking a card as default.
I do not understand this p
On Sun, May 22, 2016 at 01:42:52PM -0700, Steve Muckle wrote:
> On Sun, May 22, 2016 at 12:39:12PM +0200, Peter Zijlstra wrote:
> > On Fri, May 20, 2016 at 05:53:41PM +0530, Shilpasri G Bhat wrote:
> > >
> > > Below are the comparisons by disabling watchdog.
> > > Both schedutil and ondemand have
On Tue, Jan 19, 2016 at 11:28:56AM +0530, Ganapatrao Kulkarni wrote:
> On Mon, Jan 18, 2016 at 11:11 PM, David Daney wrote:
> > On 01/18/2016 08:36 AM, Ganapatrao Kulkarni wrote:
> >>
> >> update numa_node of device associated with pci bus.
> >> moved down devm_kzalloc to allocate from node memory
On Tue, Nov 18, 2014 at 11:30:11AM +, Arnd Bergmann wrote:
> On Tuesday 18 November 2014 19:17:32 Yijing Wang wrote:
> > On 2014/11/17 22:13, Arnd Bergmann wrote:
> > > On Monday 17 November 2014 18:21:34 Yijing Wang wrote:
> > >> This series is based Linux 3.18-rc1 and Lorenzo Pieralisi's
> >
On Mon, Nov 17, 2014 at 10:21:43AM +, Yijing Wang wrote:
> From: Yijing Wang
>
> Signed-off-by: Yijing Wang
> ---
> drivers/pci/host-bridge.c |1 +
> include/linux/pci.h |2 ++
> 2 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/pci/host-bridge.c b/dri
On Mon, Nov 17, 2014 at 10:21:48AM +, Yijing Wang wrote:
> Signed-off-by: Yijing Wang
> ---
> arch/arm/include/asm/mach/pci.h |9 +
> arch/arm/kernel/bios32.c|8 ++--
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/mach/pc
On Tue, Oct 14, 2014 at 08:53:00AM +0100, Preeti U Murthy wrote:
> We hard code the metrics relevant for cpuidle states in the kernel today.
> Instead pick them up from the device tree so that they remain relevant
> and updated for the system that the kernel is running on.
>
> Cc: linux...@vger.ke
On Wed, Oct 15, 2014 at 04:06:52AM +0100, Yijing Wang wrote:
> Saving msi chip in pci_sys_data can make pci bus and
> devices don't need to know msi chip detail, it also
> make pci enumeration code be decoupled from msi chip.
> In fact, all pci devices under the same pci hostbridge
> share same msi
On Wed, Aug 28, 2013 at 08:46:38PM +0100, Grant Likely wrote:
> On Thu, 22 Aug 2013 14:59:30 +0100, Mark Rutland wrote:
> > On Mon, Aug 19, 2013 at 02:56:10PM +0100, Sudeep KarkadaNagesha wrote:
> > > On 19/08/13 14:02, Rob Herring wrote:
> > > > On 08/19/2013 05:19 AM, Mark Rutland wrote:
> > > >
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