Hi Bjorn,
I am very sorry, The mail was filtered to another directory, I did not
notice update. The next versions will include these updates.
Thanks,
Minghuan
On 01/09/2014 08:12 AM, Bjorn Helgaas wrote:
On Wed, Jan 08, 2014 at 03:58:08PM -0600, Scott Wood wrote:
On Wed, 2014-01-08 at 13:0
Hi Scott,
please see my comments inline.
On 01/09/2014 05:58 AM, Scott Wood wrote:
On Wed, 2014-01-08 at 13:01 +0800, Minghuan Lian wrote:
PowerPC uses structure pci_controller to describe PCI controller,
but ARM uses structure pci_sys_data. In order to support PowerPC
and ARM simultaneously,
On 01/04/2014 06:19 AM, Scott Wood wrote:
On Wed, Oct 23, 2013 at 06:41:24PM +0800, Minghuan Lian wrote:
PowerPC uses structure pci_controller to describe PCI controller,
but ARM uses structure pci_sys_data. In order to support PowerPC
and ARM simultaneously, the patch adds a structure fsl_pci t
HI Scott,
please see my comments inline.
On 01/04/2014 06:33 AM, Scott Wood wrote:
On Wed, Oct 23, 2013 at 06:41:25PM +0800, Minghuan Lian wrote:
The patch adds PCI indirect read/write functions. The main code
is ported from arch/powerpc/sysdev/indirect_pci.c. We use general
IO API iowrite32be
Hi Scott,
I think we should reverse this commit
0f1741c74aa6794b1c7fbdd19f26a4f2377a11c6.
PCI controller driver is a platform driver supports probe and remove,
when removing the driver we should call mpc85xx_pci_err_remove() to free EDAC
PCI resource.
Thanks,
Minghuan
On 01/04/2014 06:16 AM,
Hi Kumar,
please see my comment inline.
On 10/24/2013 12:11 PM, Kumar Gala wrote:
On Oct 23, 2013, at 5:41 AM, Minghuan Lian wrote:
PowerPC uses structure pci_controller to describe PCI controller,
but ARM uses structure pci_sys_data. In order to support PowerPC
and ARM simultaneously, the pa
Hi Timur,
Thanks for your comments.
How about PCI_FSL_COMMON?
Thanks,
Minghuan
On 09/30/2013 07:56 AM, Timur Tabi wrote:
On Wed, Sep 18, 2013 at 6:02 AM, Minghuan Lian
wrote:
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 38f3b7e..6fd6348 100644
--- a/arch/powerpc/Kconfig
+
Hi Scott,
please see my comments inline.
On 09/28/2013 12:54 AM, Scott Wood wrote:
On Wed, 2013-09-18 at 19:02 +0800, Minghuan Lian wrote:
@@ -592,6 +719,7 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs)
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
struct device_n
Hi All,
Can anyone comment on my code or help to pick up?
Thanks,
Minghuan
On 09/18/2013 07:02 PM, Minghuan Lian wrote:
The Freescale's Layerscape series processors will use the same PCI
controller but change cores from PowerPC to ARM. This patch is to
rework FSL PCI driver to support PowerPC
Hi Scott,
Thanks for your comments.
please see my replies in line.
On 09/17/2013 08:05 AM, Scott Wood wrote:
On Thu, 2013-09-12 at 18:07 +0800, Minghuan Lian wrote:
The Freescale's Layerscape series processors will use the same PCI
controller but change cores from PowerPC to ARM. This patch i
Hi Scott,
Thanks for your comments, please see my replies inline.
On 08/24/2013 05:45 AM, Scott Wood wrote:
On Mon, 2013-08-19 at 20:23 +0800, Minghuan Lian wrote:
The Freescale's Layerscape series processors will use ARM cores.
The LS1's PCIe controllers is the same as T4240's. So it's better
Hi Scott,
please see my comments inline.
On 06/18/2013 08:18 AM, Scott Wood wrote:
On 06/17/2013 12:36:50 AM, Lian Minghuan-b31939 wrote:
Hi Scott,
please see my comments inline.
On 06/15/2013 06:13 AM, Scott Wood wrote:
On 06/14/2013 02:15:59 AM, Minghuan Lian wrote:
1. Only MSIIR1 can
On 06/18/2013 08:42 AM, Scott Wood wrote:
On 06/17/2013 07:28:07 PM, Scott Wood wrote:
On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
+compatible = "fsl,mpic-msi";
+reg = <0x41600 0x200 0x44140 4>;
Why 0x200?
[Minghuan] The offsets of the MSIA registers are
Hi Soctt,
please see my comments inline.
On 06/18/2013 08:15 AM, Scott Wood wrote:
On 06/16/2013 10:00:01 PM, Lian Minghuan-b31939 wrote:
Hi Scott,
please see my comments inline.
On 06/15/2013 06:09 AM, Scott Wood wrote:
On 06/14/2013 02:15:56 AM, Minghuan Lian wrote:
diff --git a/arch
Hi Scott,
please see my comments inline.
On 06/15/2013 06:13 AM, Scott Wood wrote:
On 06/14/2013 02:15:59 AM, Minghuan Lian wrote:
1. Only MSIIR1 can index 16 MSI registers, but when using MSIIR1
the IRQs of a register are not continuous. for example, the first
register irq values are 0x0, 0x1
On 06/15/2013 06:10 AM, Scott Wood wrote:
On 06/14/2013 02:15:58 AM, Minghuan Lian wrote:
For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. For the
first register, when using MSIIR we will get the irqs 0x0 0x1 0x2
...0x1f, bu
Hi Soctt,
please see my comments.
On 06/15/2013 06:06 AM, Scott Wood wrote:
On 06/14/2013 02:15:57 AM, Minghuan Lian wrote:
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses diffe
Hi Scott,
please see my comments inline.
On 06/15/2013 06:09 AM, Scott Wood wrote:
On 06/14/2013 02:15:56 AM, Minghuan Lian wrote:
@@ -421,10 +440,29 @@ static int fsl_of_msi_probe(struct
platform_device *dev)
}
msi->msiir_offset =
features->msiir_offset + (res.
Hi Scott,
please see my comments.
On 06/15/2013 05:53 AM, Scott Wood wrote:
On 06/14/2013 03:39:26 PM, Scott Wood wrote:
On 06/14/2013 02:15:55 AM, Minghuan Lian wrote:
+msi0: msi@41600 {
+compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
More specific compatibles come first -- and I do
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