evice remove
bus: fsl-mc: Make remove function return void
Thanks for the series, Uwe. Did a quick boot test with ACPI, so:
Reviewed-by: Laurentiu Tudor
Tested-by: Laurentiu Tudor
: Christophe Leroy
Acked-by: Laurentiu Tudor
---
drivers/tty/ehv_bytechan.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/ehv_bytechan.c b/drivers/tty/ehv_bytechan.c
index 19d32cb6af84..8595483f4697 100644
--- a/drivers/tty/ehv_bytechan.c
+++ b/drivers
ixes in schema]
Signed-off-by: Laurentiu Tudor
---
Changes in v4:
- use $ref to point to fsl,qoriq-mc-dpmac binding
Changes in v3:
- dropped duplicated "fsl,qoriq-mc-dpmac" schema and replaced with
reference to it
- fixed a dt_binding_check warning
Changes in v2:
- fixed erro
ixes in schema]
Signed-off-by: Laurentiu Tudor
---
Changes in v3:
- dropped duplicated "fsl,qoriq-mc-dpmac" schema and replaced with
reference to it
- fixed a dt_binding_check warning
Changes in v2:
- fixed errors reported by yamllint
- dropped multiple unnecessary quotes
- used sch
On 11/10/2020 7:20 PM, Rob Herring wrote:
> On Mon, Nov 9, 2020 at 4:11 PM Rob Herring wrote:
>>
>> On Mon, 09 Nov 2020 12:46:35 +0200, Laurentiu Tudor wrote:
>>> From: Ionut-robert Aron
>>>
>>> Convert fsl,qoriq-mc to YAML in order to automate the
ixes in schema]
Signed-off-by: Laurentiu Tudor
---
Changes in v2:
- fixed errors reported by yamllint
- dropped multiple unnecessary quotes
- used schema instead of text in description
- added constraints on dpmac reg property
.../devicetree/bindings/misc/fsl,qoriq-mc.txt |
From: Ionut-robert Aron
Convert fsl,dpaa2-console to YAML in order to automate the
verification process of dts files.
Signed-off-by: Ionut-robert Aron
Signed-off-by: Laurentiu Tudor
---
Changes in v2:
- add missing additionalProperties
.../bindings/misc/fsl,dpaa2-console.txt | 11
Hi Rob,
On 11/5/2020 9:17 PM, Rob Herring wrote:
> On Thu, Nov 05, 2020 at 04:11:14PM +0200, Laurentiu Tudor wrote:
>> From: Ionut-robert Aron
>>
>> Convert fsl,qoriq-mc to YAML in order to automate the verification
>> process of dts files. In addition, update MAI
ixes in schema]
Signed-off-by: Laurentiu Tudor
---
.../devicetree/bindings/misc/fsl,qoriq-mc.txt | 196
.../bindings/misc/fsl,qoriq-mc.yaml | 218 ++
.../ethernet/freescale/dpaa2/overview.rst | 5 +-
MAINTAINERS |
From: Ionut-robert Aron
Convert fsl,dpaa2-console to YAML in order to automate the
verification process of dts files.
Signed-off-by: Ionut-robert Aron
Signed-off-by: Laurentiu Tudor
---
.../bindings/misc/fsl,dpaa2-console.txt | 11 -
.../bindings/misc/fsl,dpaa2-console.yaml
Hi,
Thanks for finding this. Comment inline.
On 10/14/2020 10:27 AM, Yi Wang wrote:
> From: Hao Si
>
> The local variable 'cpumask_t mask' is in the stack memory, and its address
> is assigned to 'desc->affinity' in 'irq_set_affinity_hint()'.
> But the memory area where this variable is located
Hello,
On 10.03.2020 06:44, Michael Ellerman wrote:
Christophe Leroy writes:
Le 07/03/2020 à 09:42, Christophe Leroy a écrit :
Le 06/03/2020 à 20:05, Nick Desaulniers a écrit :
As a heads up, our CI went red last night, seems like a panic from
free_initmem? Is this a known issue?
Thanks f
On 25.02.2020 22:56, Stephen Rothwell wrote:
Hi Laurentiu,
On Tue, 25 Feb 2020 11:54:17 +0200 Laurentiu Tudor
wrote:
On 21.02.2020 01:57, Stephen Rothwell wrote:
On Thu, 16 Jan 2020 11:37:14 +1100 Stephen Rothwell
wrote:
On Wed, 15 Jan 2020 14:01:35 -0600 Scott Wood wrote:
On
I've tested it too, so please feel free to add a:
Tested-by: Laurentiu Tudor
---
Best Regards, Laurentiu
prediction resistance bits.
>
> Signed-off-by: Andrei Botila
Acked-by: Laurentiu Tudor
> ---
> drivers/bus/fsl-mc/fsl-mc-bus.c | 33 +
> include/linux/fsl/mc.h | 16
> 2 files changed, 33 insertions(+), 16 deletions(-)
>
&
entry if already running in AS=1.
Fixes: d9e1831a4202 ("powerpc/85xx: Load all early TLB entries at once")
Signed-off-by: Laurentiu Tudor
Cc: sta...@vger.kernel.org
---
arch/powerpc/mm/nohash/tlb_low.S | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/
from drivers/tty/ehv_bytechan.c:24:
> arch/powerpc/include/asm/epapr_hcalls.h:300:20: warning: array subscript 3
> is outside array bounds of ‘const char[1]’ [-Warray-bounds]
> 300 | r8 = be32_to_cpu(p[3]);
> include/uapi/linux/byteorder/big_endian.h:40:51: note: in definition of
> macro ‘__be32_to_cpu’
>40 | #define __be32_to_cpu(x) ((__force __u32)(__be32)(x))
> | ^
> arch/powerpc/include/asm/epapr_hcalls.h:300:7: note: in expansion of macro
> ‘be32_to_cpu’
> 300 | r8 = be32_to_cpu(p[3]);
> | ^~~
> drivers/tty/ehv_bytechan.c:166:13: note: while referencing ‘data’
> 166 | static void ehv_bc_udbg_putc(char c)
> | ^~~~
>
> Signed-off-by: Stephen Rothwell
> ---
Tested-by: Laurentiu Tudor
---
Best Regards, Laurentiu
Michael Ellerman made a call for volunteers from NXP to maintain
this driver and I offered myself.
Signed-off-by: Laurentiu Tudor
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4017e6b760be..62082e5f7101 100644
--- a/MAINTAINERS
+++ b
On 14.01.2020 03:10, Michael Ellerman wrote:
> Laurentiu Tudor writes:
>> Hello,
>>
>> On 13.01.2020 15:48, Timur Tabi wrote:
>>> On 1/13/20 6:26 AM, Michael Ellerman wrote:
>>>> I've never heard of it, and I have no idea how to test it.
>>
Hello,
On 13.01.2020 15:48, Timur Tabi wrote:
> On 1/13/20 6:26 AM, Michael Ellerman wrote:
>> I've never heard of it, and I have no idea how to test it.
>>
>> It's not used by qemu, I guess there is/was a Freescale hypervisor that
>> used it.
>
> Yes, there is/was a Freescale hypervisor that I a
> -Original Message-
> From: Andreas Färber
> Sent: Friday, May 31, 2019 8:04 PM
>
> Hello Laurentiu,
>
> Am 31.05.19 um 18:46 schrieb Laurentiu Tudor:
> >> -Original Message-
> >> From: Andreas Färber
> >> Sent: Friday, May 31, 2
> -Original Message-
> From: Christoph Hellwig
> Sent: Friday, May 31, 2019 7:56 PM
>
> On Fri, May 31, 2019 at 04:53:16PM +0000, Laurentiu Tudor wrote:
> > Unfortunately due to our hardware particularities we do not have
> alternatives. This is also the case fo
Hi Christoph,
> -Original Message-
> From: Christoph Hellwig
> Sent: Friday, May 31, 2019 7:32 PM
>
> On Thu, May 30, 2019 at 05:19:50PM +0300, laurentiu.tu...@nxp.com wrote:
> > +static phys_addr_t dpaa_iova_to_phys(const struct dpaa_priv *priv,
> > +dma_
Hello Andreas,
> -Original Message-
> From: Andreas Färber
> Sent: Friday, May 31, 2019 7:15 PM
>
> Hi Laurentiu,
>
> Am 30.05.19 um 16:19 schrieb laurentiu.tu...@nxp.com:
> > This patch series contains several fixes in preparation for SMMU
> > support on NXP LS1043A and LS1046A chips.
Hello,
> -Original Message-
> From: David Miller
> Sent: Friday, May 31, 2019 1:09 AM
>
> From: laurentiu.tu...@nxp.com
> Date: Thu, 30 May 2019 17:19:45 +0300
>
> > Depends on this pull request:
> >
> >
> http://lists.infradead.org/pipermail/linux-arm-kernel/2019-May/653554.html
>
> I
From: Laurentiu Tudor
Add an API that retrieves the 'struct device' that the specified fman
port probed against. The new API will be used in a subsequent iommu
enablement related patch.
Signed-off-by: Laurentiu Tudor
Acked-by: Madalin Bucur
---
drivers/net/ethernet/freescale/fman/f
From: Laurentiu Tudor
liodn base registers are specific to PAMU based NXP systems and on SMMU
based ones are reserved. Don't access them if PAMU is compiled in.
Signed-off-by: Laurentiu Tudor
---
drivers/net/ethernet/freescale/fman/fman.c | 6 +-
1 file changed, 5 insertions(
From: Laurentiu Tudor
This patch series contains several fixes in preparation for SMMU
support on NXP LS1043A and LS1046A chips. Once these get picked up,
I'll submit the actual SMMU enablement patches consisting in the
required device tree changes.
This patch series contains only part o
From: Laurentiu Tudor
The dma transactions initiator is the rx fman port so that's the device
that the dma mappings should be done. Previously the mappings were done
through the MAC device which makes no sense because it's neither dma-able
nor connected in any way to smmu.
Sig
From: Laurentiu Tudor
Enabling SMMU altered the order of device probing causing the dpaa1
ethernet driver to get probed before qbman and causing a boot crash.
Add predictability in the probing order by deferring the ethernet
driver probe after qbman and portals by using the recently introduced
From: Laurentiu Tudor
The driver relies on the no longer valid assumption that dma addresses
(iovas) are identical to physical addressees and uses phys_to_virt() to
make iova -> vaddr conversions. Fix this by adding a function that does
proper iova -> phys conversions using the iommu a
From: Laurentiu Tudor
The driver relies on the no longer valid assumption that dma addresses
(iovas) are identical to physical addressees and uses phys_to_virt() to
make iova -> vaddr conversions. Fix this also for scatter-gather frames
using the iova -> phys conversion function added
From: Laurentiu Tudor
Fix issue with the entry indexing in the sg frame cleanup code being
off-by-1. This problem showed up when doing some basic iperf tests and
manifested in traffic coming to a halt.
Signed-off-by: Laurentiu Tudor
Acked-by: Madalin Bucur
Cc:
---
v3:
- added cc:stable tag
> -Original Message-
> From: Joakim Tjernlund
> Sent: Thursday, May 2, 2019 1:37 PM
>
> On Thu, 2019-05-02 at 09:05 +0000, Laurentiu Tudor wrote:
> > Hi Joakim,
> >
> > > -Original Message-
> > > From: Joakim Tjernlund
> -Original Message-
> From: Christoph Hellwig
> Sent: Saturday, April 27, 2019 7:46 PM
>
> On Sat, Apr 27, 2019 at 10:10:29AM +0300, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > The driver relies on the no longer valid assumpt
Hi Joakim,
> -Original Message-
> From: Joakim Tjernlund
> Sent: Saturday, April 27, 2019 8:11 PM
>
> On Sat, 2019-04-27 at 10:10 +0300, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > Fix issue with the entry indexing in the sg fram
From: Laurentiu Tudor
Fix issue with the entry indexing in the sg frame cleanup code being
off-by-1. This problem showed up when doing some basic iperf tests and
manifested in traffic coming to a halt.
Signed-off-by: Laurentiu Tudor
Acked-by: Madalin Bucur
---
drivers/net/ethernet/freescale
From: Laurentiu Tudor
The driver relies on the no longer valid assumption that dma addresses
(iovas) are identical to physical addressees and uses phys_to_virt() to
make iova -> vaddr conversions. Fix this also for scatter-gather frames
using the iova -> phys conversion function added
From: Laurentiu Tudor
The driver relies on the no longer valid assumption that dma addresses
(iovas) are identical to physical addressees and uses phys_to_virt() to
make iova -> vaddr conversions. Fix this by adding a function that does
proper iova -> phys conversions using the iommu a
From: Laurentiu Tudor
Enabling SMMU altered the order of device probing causing the dpaa1
ethernet driver to get probed before qbman and causing a boot crash.
Add predictability in the probing order by deferring the ethernet
driver probe after qbman and portals by using the recently introduced
From: Laurentiu Tudor
During probing, FMAN is reset thus losing all its register
settings. Backup port ICID registers before reset and restore
them after, similarly to how it's done on powerpc / PAMU based
platforms.
This also has the side effect of disabling the old code path
(liodn b
From: Laurentiu Tudor
The dma transactions initiator is the rx fman port so that's the device
that the dma mappings should be done. Previously the mappings were done
through the MAC device which makes no sense because it's neither dma-able
nor connected in any way to smmu.
Sig
From: Laurentiu Tudor
Add an API that retrieves the 'struct device' that the specified fman
port probed against. The new API will be used in a subsequent iommu
enablement related patch.
Signed-off-by: Laurentiu Tudor
Acked-by: Madalin Bucur
---
drivers/net/ethernet/freescale/fman/f
From: Laurentiu Tudor
ARM SoCs use SMMU so the liodn fixup done in the qman driver is no
longer making sense and it also breaks the ICID settings inherited
from u-boot. Do the fixups only for PPC targets.
Signed-off-by: Laurentiu Tudor
---
drivers/soc/fsl/qbman/qman_ccsr.c | 2 +-
drivers/soc
From: Laurentiu Tudor
Add a couple of new APIs to check the probing status of the required
cpu bound qman and bman portals:
'int bman_portals_probed()' and 'int qman_portals_probed()'.
They return the following values.
* 1 if qman/bman portals were all probed correctl
From: Laurentiu Tudor
This patch series contains several fixes in preparation for SMMU
support on NXP LS1043A and LS1046A chips. Once these get picked up,
I'll submit the actual SMMU enablement patches consisting in the
required device tree changes.
This patch series contains only part o
Hi Robin,
> -Original Message-
> From: Robin Murphy
> Sent: Friday, March 29, 2019 4:51 PM
>
> On 29/03/2019 14:00, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > Add a one-to-one iommu mapping for bman private data memory (FBPR).
>
From: Laurentiu Tudor
Set RI in the default kernel's MSR so that the architected way of
detecting unrecoverable machine check interrupts has a chance to work.
This is inline with the MSR setup of the rest of booke powerpc
architectures configured here.
Signed-off-by: Laurentiu Tudor
Cc
From: Laurentiu Tudor
Set SI in the default kernel's MSR so that the architected way of
detecting unrecoverable machine check interrupts has a chance to work.
This is inline with the MSR setup of the rest of booke powerpc
architectures configured here.
Signed-off-by: Laurentiu Tudor
Cc
t object region v2 command which returns both
> a base address and offset for the portal memory. The new portal
> region is identified as shareable through the addition of a new
> flag.
>
> Signed-off-by: Roy Pledge
Looks good to me:
Reviewed-by: Laurentiu Tudor
---
Best Regards,
Hi Leo,
> -Original Message-
> From: Li Yang [mailto:leoyang...@nxp.com]
> Sent: Friday, March 29, 2019 11:16 PM
>
> On Fri, Mar 29, 2019 at 9:03 AM wrote:
> >
> > From: Laurentiu Tudor
> >
> > Add a one-to-one iommu mapping for bman private data
Hi Robin,
> -Original Message-
> From: Robin Murphy [mailto:robin.mur...@arm.com]
> Sent: Friday, March 29, 2019 4:51 PM
>
> On 29/03/2019 14:00, laurentiu.tu...@nxp.com wrote:
> > From: Laurentiu Tudor
> >
> > Add a one-to-one iommu mapping for bman pri
t; On Fri, 2019-03-29 at 16:00 +0200, laurentiu.tu...@nxp.com wrote:
> >
> > From: Laurentiu Tudor
> >
> > Fix issue with the entry indexing in the sg frame cleanup code being
> > off-by-1. This problem showed up when doing some basic iperf tests and
> > mani
Hi Leo,
> -Original Message-
> From: Li Yang [mailto:leoyang...@nxp.com]
> Sent: Friday, March 29, 2019 11:50 PM
> To: Laurentiu Tudor
> Cc: Netdev ; Madalin-cristian Bucur
> ; Roy Pledge ; Camelia
> Alexandra Groza ; David Miller
> ; Linux IOMMU ;
> moder
Hi Leo,
> -Original Message-
> From: Li Yang [mailto:leoyang...@nxp.com]
> Sent: Saturday, March 30, 2019 12:07 AM
> To: Laurentiu Tudor
> Cc: Netdev ; Madalin-cristian Bucur
> ; Roy Pledge ; Camelia
> Alexandra Groza ; David Miller
> ; Linux IOMMU ;
> moder
From: Laurentiu Tudor
The driver relies on the no longer valid assumption that dma addresses
(iovas) are identical to physical addressees and uses phys_to_virt() to
make iova -> vaddr conversions. Fix this also for scatter-gather frames
using the iova -> phys conversion function added
From: Laurentiu Tudor
Add a couple of new APIs to check the probing status of the required
cpu bound qman and bman portals:
'int bman_portals_probed()' and 'int qman_portals_probed()'.
They return the following values.
* 1 if qman/bman portals were all probed correctl
From: Laurentiu Tudor
Add a one-to-one iommu mapping for bman private data memory (FBPR).
This is required for BMAN to work without faults behind an iommu.
Signed-off-by: Laurentiu Tudor
---
drivers/soc/fsl/qbman/bman_ccsr.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a
From: Laurentiu Tudor
ARM SoCs use SMMU so the liodn fixup done in the qman driver is no
longer making sense and it also breaks the ICID settings inherited
from u-boot. Do the fixups only for PPC targets.
Signed-off-by: Laurentiu Tudor
---
drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
1 file
From: Laurentiu Tudor
Add a one-to-one iommu mapping for qman private data memory areas
(FQD and PFDR). This is required for QMAN to work without faults
behind an iommu.
Signed-off-by: Laurentiu Tudor
---
drivers/soc/fsl/qbman/qman_ccsr.c | 15 +++
1 file changed, 15 insertions
From: Laurentiu Tudor
Enabling SMMU altered the order of device probing causing the dpaa1
ethernet driver to get probed before qbman and causing a boot crash.
Add predictability in the probing order by deferring the ethernet
driver probe after qbman and portals by using the recently introduced
From: Laurentiu Tudor
Prior to calling iommu_map()/iommu_unmap() page align the size or
failures such as below could happen:
iommu: unaligned: iova 0x... pa 0x... size 0x4000 min_pagesz 0x1
qman_portal 5.qman-portal: failed to iommu_map() -22
Seen when booted a kernel compiled with
From: Laurentiu Tudor
Add an API that retrieves the 'struct device' that the specified fman
port probed against. The new API will be used in a subsequent iommu
enablement related patch.
Signed-off-by: Laurentiu Tudor
Acked-by: Madalin Bucur
---
drivers/net/ethernet/freescale/fman/f
From: Laurentiu Tudor
During probing, FMAN is reset thus losing all its register
settings. Backup port ICID registers before reset and restore
them after, similarly to how it's done on powerpc / PAMU based
platforms.
This also has the side effect of disabling the old code path
(liodn b
From: Laurentiu Tudor
The dma transactions initiator is the rx fman port so that's the device
that the dma mappings should be done. Previously the mappings were done
through the MAC device which makes no sense because it's neither dma-able
nor connected in any way to smmu.
Sig
From: Laurentiu Tudor
This patch series contains several fixes in preparation for SMMU
support on NXP LS1043A and LS1046A chips. Once these get picked up,
I'll submit the actual SMMU enablement patches consisting in the
required device tree changes.
This patch series contains only part o
From: Laurentiu Tudor
Fix issue with the entry indexing in the sg frame cleanup code being
off-by-1. This problem showed up when doing some basic iperf tests and
manifested in traffic coming to a halt.
Signed-off-by: Laurentiu Tudor
Acked-by: Madalin Bucur
---
drivers/net/ethernet/freescale
From: Laurentiu Tudor
The driver relies on the no longer valid assumption that dma addresses
(iovas) are identical to physical addressees and uses phys_to_virt() to
make iova -> vaddr conversions. Fix this by adding a function that does
proper iova -> phys conversions using the iommu a
From: Laurentiu Tudor
Add a one-to-one iommu mapping for qman portal CENA register area.
This is required for QMAN stashing to work without faults behind
an iommu.
Signed-off-by: Laurentiu Tudor
---
drivers/soc/fsl/qbman/qman_portal.c | 17 +
1 file changed, 17 insertions
Hi Scott,
> -Original Message-
> On Mon, 2018-08-27 at 20:15 +0200, Christian Zigotzky wrote:
> > Hello,
> >
> > Our users tested the RC1 of kernel 4.19 on their P5020 boards today.
> > Unfortunately the USB bug still exists. With mem values bigger than
> 4096M,
> > the USB mouse and keyb
On 05/20/2018 04:49 PM, Nipun Gupta wrote:
> of_dma_configure() API expects coherent_dma_mask to be correctly
> set in the devices. This patch does the needful.
>
> Signed-off-by: Nipun Gupta
Acked-by: Laurentiu Tudor
---
Best Regards, Laurentiu
> ---
> drivers/bus/fsl-m
Hi Nipun,
On 04/27/2018 01:27 PM, Nipun Gupta wrote:
> Signed-off-by: Nipun Gupta
> ---
> drivers/bus/fsl-mc/fsl-mc-bus.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c
> index 5d8266c
wed-by: Laurentiu Tudor
---
Best Regards, Laurentiu
> drivers/bus/fsl-mc/fsl-mc-bus.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c
> index 5d8266c..624828b 100644
> ---
Hi Nipun,
On 04/30/2018 09:27 AM, Nipun Gupta wrote:
> fsl-mc bus support the new iommu-map property. Comply to this binding
> for fsl_mc bus.
>
> Signed-off-by: Nipun Gupta
This looks good to me, so:
Reviewed-By: Laurentiu Tudor
---
Best Regards, Laurentiu
> ---
> a
Hi Michael,
On 04/27/2018 09:14 AM, Michael Ellerman wrote:
> laurentiu.tu...@nxp.com writes:
>> From: Laurentiu Tudor
>>
>> Add missing "altivec unavailable" interrupt injection helper
>> thus fixing the linker error below:
>>
>>
From: Laurentiu Tudor
Add missing "altivec unavailable" interrupt injection helper
thus fixing the linker error below:
arch/powerpc/kvm/emulate_loadstore.o: In function
`kvmppc_check_altivec_disabled':
arch/powerpc/kvm/emulate_loadstore.c: undefin
Hi Jocke,
On 09/01/2017 02:32 PM, Joakim Tjernlund wrote:
> I am trying to debug a Machine Check for a P2010 (e500v2) CPU:
>
> [ 28.111816] Caused by (from MCSR=10008): Bus - Read Data Bus Error
> [ 28.117998] Oops: Machine check, sig: 7 [#1]
> [ 28.122263] P1010 RDB
> [ 28.124529] Modules
On 08/31/2017 01:52 AM, Michael Ellerman wrote:
> Hi Gregory,
>
> Gregory Fong writes:
>> Hi all,
>>
>> In arch/powerpc/sysdev/mpic.c , it looks like IRQ_TYPE_EDGE_BOTH is
>> handled the same way as IRQ_TYPE_EDGE_FALLING:
>>
>> static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned
Hi Michael,
On 07/18/2017 01:55 PM, Michael Ellerman wrote:
> laurentiu.tu...@nxp.com writes:
>
>> From: Laurentiu Tudor
>>
>> This allows building powerpc with the GENERIC_MSI_IRQ_DOMAIN
>> Kconfig by enabling the asm-generic msi.h in Kbuild. Without
>>
Hi Michael,
On 06/30/2017 01:08 PM, Michael Ellerman wrote:
> Hi Laurentiu,
>
> laurentiu.tu...@nxp.com writes:
>> From: Laurentiu Tudor
>>
>> This allows building powerpc with the GENERIC_MSI_IRQ Kconfig
>> by enabling the asm-generic msi.h in Kbuild. Witho
-Original Message-
From: Michael Ellerman [mailto:m...@ellerman.id.au]
Sent: Friday, April 07, 2017 4:22 PM
To: Laurentiu Tudor ; Horia Geantă
; Herbert Xu ; Scott Wood
; Roy Pledge
Cc: Claudiu Manoil ; Cristian Stoica
; Dan Douglass ;
linux-arm-ker...@lists.infradead.org; Vakul
On 04/05/2017 01:06 PM, Michael Ellerman wrote:
> Laurentiu Tudor writes:
>
>> Hi Michael,
>>
>> Just a couple of basic things to check:
>>- was the dtb updated to the newest?
>
> Possibly not, it's an automated build/boot, I'll have to check
Hi Michael,
Just a couple of basic things to check:
- was the dtb updated to the newest?
- is the qman node present? This should be easily visible in
/proc/device-tree/soc@ffe00/qman@318000.
---
Best Regards, Laurentiu
On 04/04/2017 08:03 AM, Michael Ellerman wrote:
> Horia Geantă writ
Hi,
Some more information on the crash, inline.
On 02/17/2017 02:18 PM, Aneesh Kumar K.V wrote:
> laurentiu.tu...@nxp.com writes:
>
>> From: Laurentiu Tudor
>>
>> On 32-bit book-e machines, hugepd_ok() does not take
>> into account null hugepd values, causing this
Hi Wolfgang,
Thanks for reporting!
On 02/28/2017 01:47 PM, Wolfgang Ocker wrote:> On Tue, 2017-02-28 at
10:57 +0100, Wolfgang Ocker wrote:
>> With kernel v4.10.1 and huge tlb enabled (CONFIG_HUGETLBFS=y) I see
>> the
>> following oops on a P1010:
>
> Just saw that there is already a fix:
t handling to pass
> the number of valid ranges in the property as the function return code
> rather than passing it by reference. With this change, gcc can see that
> we don't evaluate the cell numbers for an missing ranges property.
>
> Signed-off-by: Arnd Bergmann
Looks good to me, i've tested it and did not see any issues, so here's an:
Acked-by: Laurentiu Tudor
---
Thanks & Best Regards, Laurentiu
On 02/17/2017 02:18 PM, Aneesh Kumar K.V wrote:
> laurentiu.tu...@nxp.com writes:
>
>> From: Laurentiu Tudor
>>
>> On 32-bit book-e machines, hugepd_ok() does not take
>> into account null hugepd values, causing this crash at boot:
>>
>> Unable t
On 02/17/2017 12:08 PM, Scott Wood wrote:
> On Thu, 2017-02-16 at 09:11 -0600, laurentiu.tu...@nxp.com wrote:
>> From: Laurentiu Tudor
>>
>> On 32-bit book-e machines, hugepd_ok() does not take
>> into account null hugepd values, causing this crash at boot:
>
>
Hi Thomas,
On 02/01/2017 11:46 AM, Thomas De Schampheleire wrote:
> On Wed, Jan 25, 2017 at 10:46 AM, Thomas De Schampheleire
> wrote:
>> Hi,
>>
>> We are experiencing kernel panics of the type "Unable to handle kernel paging
>> request for instruction fetch" but are stuck in our analysis. We wou
On 10/07/2015 06:48 AM, Scott Wood wrote:
> Use an AS=1 trampoline TLB entry to allow all normal TLB1 entries to
> be loaded at once. This avoids the need to keep the translation that
> code is executing from in the same TLB entry in the final TLB
> configuration as during early boot, which in tur
The register is not currently used in the base kernel
but will be in a forthcoming kvm patch.
Signed-off-by: Laurentiu Tudor
---
arch/powerpc/include/asm/reg_booke.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm
On 08/10/2015 10:48 AM, Ran Shalit wrote:
> Hello,
>
> MPC8349 has general IRQ numbered 0-7,
> It is required to bind these IRQs with some routine , i.e. they are
> not used with any specific driver.
>
> - Should they be configured as gpios in device tree so that we can use
> the gpio as irq in l
On 05/26/2015 08:10 AM, Anton Blanchard wrote:
> When we take a PMU exception or a software event we call
> perf_read_regs(). This overloads regs->result with a boolean that
> describes if we should use the sampled instruction address register
> (SIAR) or the regs.
>
> If the exception is in kerne
Hi Sandeep,
Small nit inside.
On 04/02/2015 01:47 PM, sand...@freescale.com wrote:
> From: Sandeep Singh
>
> This controller is available on many Freescale SOCs like MPC8315, P1020,
> P1010,
> P1022 and P1024
>
> Signed-off-by: Sandeep Singh
> Signed-off-by: Poonam Aggrwal
> ---
> Document
Hi Michael,
Comment inline.
On 10/10/2014 11:04 AM, Michael Ellerman wrote:
> As demonstrated in the previous commit, the failure message from the msi
> bitmap selftests is a bit subtle, it's easy to miss a failure in a busy
> boot log.
>
> So drop our check() macro and use WARN_ON() instead. Th
Hi Jingchang,
On 09/23/2014 09:46 AM, Jingchang Lu wrote:
> The IP is shared by PPC and ARM, this renames it to qoriq for better
> represention, and this also adds the CLK_OF_DECLARE support for being
> initialized by of_clk_init() on ARM.
>
I think you need to also update drivers/cpufreq/Kconfi
Hi Michael,
Minor comment inline.
On 09/18/2014 11:26 AM, Michael Neuling wrote:
> From: Ian Munsie
>
> Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
> to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This wastes
> a
> lot of IRQs which can be a
On 09/19/2014 11:16 PM, Scott Wood wrote:
> On Thu, 2014-09-18 at 18:26 +1000, Michael Neuling wrote:
>> From: Ian Munsie
>>
>> Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
>> to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This
>> wastes a
>> lo
On 09/19/2014 11:19 PM, Scott Wood wrote:
> On Fri, 2014-09-19 at 15:16 -0500, Scott Wood wrote:
>> On Thu, 2014-09-18 at 18:26 +1000, Michael Neuling wrote:
>>> From: Ian Munsie
>>>
>>> Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation
>>> requests
>>> to the nearest power of
On 09/08/2014 04:29 PM, Grant Likely wrote:
> On Wed, 27 Aug 2014 17:09:39 +0300, Laurentiu Tudor
> wrote:
>> Simply swap of_alias and of_chosen initialization so
>> that of_alias ends up read first. This must be done
>> because it is accessed couple of lines below when
1 - 100 of 116 matches
Mail list logo
