From: Michael Neuling
Document support for nested KVM on POWER using the existing API as well
as the new PAPR API. This includes the new HCALL interface and how it
used by KVM.
Signed-off-by: Michael Neuling
Signed-off-by: Jordan Niethe
---
v2:
- Separated into individual patch
v3:
- Fix
d to be loaded again.
Tested-by: Sachin Sant
Signed-off-by: Vaibhav Jain
Signed-off-by: Gautam Menghani
Signed-off-by: Kautuk Consul
Signed-off-by: Amit Machhiwal
Signed-off-by: Jordan Niethe
---
v2:
- Declare op structs as static
- Guatam: Use expressions in switch case with local variables
eries_rpt_invalidate() to
match that. Update the callers of pseries_rpt_invalidate() to also take
an unsigned long if they take an lpid value.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
v4:
- Use u64
- Change format strings instead of casting
---
arch/powerpc/include/asm/k
the value of elements and parsing buffers. This will be used
later by the nestedv2 guest support.
Signed-off-by: Jordan Niethe
---
v2:
- Add missing #ifdef CONFIG_VSXs
- Move files from lib/ to kvm/
- Guard compilation on CONFIG_KVM_BOOK3S_HV_POSSIBLE
- Use kunit for guest state buffer test
not currently present.
kvmppc_set_msr_hv() already exists, it is used for the
kvmppc_ops::set_msr callback.
Introduce a low level accessor __kvmppc_{s,g}et_msr_hv() that simply
gets and sets shregs::msr. This will be extend for Nested APIv2 support.
Signed-off-by: Jordan Niethe
---
v4:
- New
Introduce accessor generator macros for Book3S HV VCPU registers. Use
the accessor functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan
Introduce accessor generator macros for VCORE registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
Introduce accessor generator macros for VCPU registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consistent naming convention.
Reviewed-by: Nicholas Piggin
Signed-off-by: Jordan Niethe
---
v3:
- New to
state.
Signed-off-by: Gautam Menghani
Signed-off-by: Jordan Niethe
---
v3:
- Guatam: Pass vector elements by reference
v4:
- Split into unique patch
---
arch/powerpc/include/asm/kvm_book3s.h | 55
arch/powerpc/include/asm/kvm_booke.h | 10
arch/powerpc/kvm/book3s.c
Always use the GPR accessor functions. This will be important later for
Nested APIv2 support which requires additional functionality for
accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
---
v4:
- Split into unique patch
---
arch/powerpc/kvm/book3s_64_vio.c | 4 ++--
arch
v/20230905034658.82835-1-jniet...@gmail.com/
Jordan Niethe (10):
KVM: PPC: Always use the GPR accessors
KVM: PPC: Introduce FPR/VR accessor functions
KVM: PPC: Rename accessor generator macros
KVM: PPC: Use accessors for VCPU registers
KVM: PPC: Use accessors for VCORE registers
KVM: PPC: Boo
From: Michael Neuling
Document support for nested KVM on POWER using the existing API as well
as the new PAPR API. This includes the new HCALL interface and how it
used by KVM.
Signed-off-by: Michael Neuling
Signed-off-by: Jordan Niethe
---
v2:
- Separated into individual patch
v3:
- Fix
d to be loaded again.
Signed-off-by: Vaibhav Jain
Signed-off-by: Gautam Menghani
Signed-off-by: Kautuk Consul
Signed-off-by: Amit Machhiwal
Signed-off-by: Jordan Niethe
---
v2:
- Declare op structs as static
- Guatam: Use expressions in switch case with local variables
- Do not use the PVR fo
eries_rpt_invalidate() to
match that. Update the callers of pseries_rpt_invalidate() to also take
an unsigned long if they take an lpid value.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
v4:
- Use u64
- Change format strings instead of casting
---
arch/powerpc/include/asm/k
the value of elements and parsing buffers. This will be used
later by the nestedv2 guest support.
Signed-off-by: Jordan Niethe
---
v2:
- Add missing #ifdef CONFIG_VSXs
- Move files from lib/ to kvm/
- Guard compilation on CONFIG_KVM_BOOK3S_HV_POSSIBLE
- Use kunit for guest state buffer test
not currently present.
kvmppc_set_msr_hv() already exists, it is used for the
kvmppc_ops::set_msr callback.
Introduce a low level accessor __kvmppc_{s,g}et_msr_hv() that simply
gets and sets shregs::msr. This will be extend for Nested APIv2 support.
Signed-off-by: Jordan Niethe
---
v4:
- New
Introduce accessor generator macros for Book3S HV VCPU registers. Use
the accessor functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan
Introduce accessor generator macros for VCORE registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
Introduce accessor generator macros for VCPU registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consistent naming convention.
Reviewed-by: Nicholas Piggin
Signed-off-by: Jordan Niethe
---
v3:
- New to
state.
Signed-off-by: Jordan Niethe
---
v4:
- Split into unique patch
---
arch/powerpc/include/asm/kvm_book3s.h | 55
arch/powerpc/include/asm/kvm_booke.h | 10
arch/powerpc/kvm/book3s.c | 16 +++---
arch/powerpc/kvm/emulate_loadstore.c | 2 +-
arch/powerpc
Always use the GPR accessor functions. This will be important later for
Nested APIv2 support which requires additional functionality for
accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
---
v4:
- Split into unique patch
---
arch/powerpc/kvm/book3s_64_vio.c | 4 ++--
arch
tps://lore.kernel.org/linuxppc-dev/20230807014553.1168699-1-jniet...@gmail.com/
Jordan Niethe (10):
KVM: PPC: Always use the GPR accessors
KVM: PPC: Introduce FPR/VR accessor functions
KVM: PPC: Rename accessor generator macros
KVM: PPC: Use accessors for VCPU registers
KVM: PPC: Use a
On 15/8/23 8:45 pm, Michael Ellerman wrote:
"Nicholas Piggin" writes:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
The LPID register is 32 bits long. The host keeps the lpids for each
guest in an unsigned word struct kvm_arch. Currently, LPIDs are already
On 14/8/23 6:27 pm, Nicholas Piggin wrote:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consist
On 14/8/23 6:15 pm, David Laight wrote:
From: Jordan Niethe
Sent: 07 August 2023 02:46
The LPID register is 32 bits long. The host keeps the lpids for each
guest in an unsigned word struct kvm_arch. Currently, LPIDs are already
limited by mmu_lpid_bits and KVM_MAX_NESTED_GUESTS_SHIFT.
The
On 14/8/23 6:12 pm, Nicholas Piggin wrote:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
The LPID register is 32 bits long. The host keeps the lpids for each
guest in an unsigned word struct kvm_arch. Currently, LPIDs are already
limited by mmu_lpid_bits and
On 14/8/23 6:08 pm, Nicholas Piggin wrote:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
There are already some getter and setter functions used for accessing
vcpu register state, e.g. kvmppc_get_pc(). There are also more
complicated examples that are generated by macros like
From: Michael Neuling
Document support for nested KVM on POWER using the existing API as well
as the new PAPR API. This includes the new HCALL interface and how it
used by KVM.
Signed-off-by: Michael Neuling
Signed-off-by: Jordan Niethe
---
v2:
- Separated into individual patch
v3:
- Fix
d to be loaded again.
Signed-off-by: Vaibhav Jain
Signed-off-by: Gautam Menghani
Signed-off-by: Kautuk Consul
Signed-off-by: Amit Machhiwal
Signed-off-by: Jordan Niethe
---
v2:
- Declare op structs as static
- Guatam: Use expressions in switch case with local variables
- Do not use the PVR fo
eries_rpt_invalidate() to
match that. Update the callers of pseries_rpt_invalidate() to also take
an unsigned long if they take an lpid value.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
---
arch/powerpc/include/asm/kvm_book3s.h | 10 +-
arch/powerpc/include/asm/kvm_book3s
the value of elements and parsing buffers. This will be used
later by the nestedv2 guest support.
Signed-off-by: Jordan Niethe
---
v2:
- Add missing #ifdef CONFIG_VSXs
- Move files from lib/ to kvm/
- Guard compilation on CONFIG_KVM_BOOK3S_HV_POSSIBLE
- Use kunit for guest state buffer test
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consistent naming convention.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
---
arch/powerpc/include/asm
ers. These wrappers will
be augmented for supporting Nestedv2 guests later.
Signed-off-by: Gautam Menghani
Signed-off-by: Jordan Niethe
---
v3:
- Do not add a helper for pvr
- Use an expression when declaring variable in case
- Squash in all getters and setters
- Guatam: Pass vector re
nuxppc-dev/20230508072332.2937883-1-...@linux.vnet.ibm.com/
- v2:
https://lore.kernel.org/linuxppc-dev/20230605064848.12319-1-...@linux.vnet.ibm.com/
Jordan Niethe (5):
KVM: PPC: Use getters and setters for vcpu register state
KVM: PPC: Rename accessor generator macros
KVM: PPC: Add helper library
powernv: Fix endian issues in OPAL ICS
backend") used a new variable 'oserver' as the parameter to
opal_get_xive() instead of 'server' for endian correctness. It also
removed 'server' from the error message for the call to opal_get_xive().
It was commit bf8e0
On 8/6/23 10:34 pm, Kautuk Consul wrote:
Need at least a little context in the commit message itself:
"Enable ring-based dirty memory tracking on ppc64:"
- Enable CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL as ppc64 is weakly
ordered.
- Enable CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP because the
On 26/6/23 5:04 pm, Mahesh Salgaonkar wrote:
opal_prd_msg_notifier extracts the opal prd message size from the message
header and uses it for allocating opal_prd_msg_queue_item that includes
the correct message size to be copied. However, while running under
CONFIG_FORTIFY_SOURCE=y, it trigger
On Wed, Jun 7, 2023 at 7:09 PM Nicholas Piggin wrote:
[snip]
>
> You lost your comments.
Thanks
>
> > diff --git a/arch/powerpc/include/asm/kvm_book3s.h
> > b/arch/powerpc/include/asm/kvm_book3s.h
> > index 0ca2d8b37b42..c5c57552b447 100644
> > --- a/arch/powerpc/include/asm/kvm_book3s.h
> > ++
On Wed, Jun 7, 2023 at 6:27 PM Nicholas Piggin wrote:
[snip]
>
> This is a tour de force in one of these things, so I hate to be
> the "me smash with club" guy, but what if you allocated buffers
> with enough room for all the state (or 99% of cases, in which
> case an overflow would make an hcall)
On Wed, Jun 7, 2023 at 5:56 PM Nicholas Piggin wrote:
[snip]
>
> Is there a particular reason some reg sets are broken into their own
> patches? Looking at this hunk you think the VR one got missed, but it's
> in its own patch.
>
> Not really a big deal but I wouldn't mind them all in one patch. O
On Wed, Jun 7, 2023 at 5:53 PM Nicholas Piggin wrote:
[snip]
>
> The general idea is fine, some of the names could use a bit of
> improvement. What's a BOOK3S_WRAPPER for example, is it not a
> VCPU_WRAPPER, or alternatively why isn't a VCORE_WRAPPER Book3S
> as well?
Yeah the names are not great
On Wed, Jun 7, 2023 at 3:54 PM Nicholas Piggin wrote:
>
> On Mon Jun 5, 2023 at 4:48 PM AEST, Jordan Niethe wrote:
> > There is existing support for nested guests on powernv hosts however the
> > hcall interface this uses is not support by other PAPR hosts.
>
> I kind
On Wed, Jun 7, 2023 at 3:38 PM Gautam Menghani wrote:
>
> On Mon, Jun 05, 2023 at 04:48:48PM +1000, Jordan Niethe wrote:
> > From: Michael Neuling
>
> Hi,
> There are some minor typos in the documentation pointed out below
Thank you, will correct in the n
. This existing API is still supported.
Signed-off-by: Jordan Niethe
---
v2:
- Declare op structs as static
- Use expressions in switch case with local variables
- Do not use the PVR for the LOGICAL PVR ID
- Handle emul_inst as now a double word
- Use new GPR(), etc macros
- Determine
From: Michael Neuling
Document support for nested KVM on POWER using the existing API as well
as the new PAPR API. This includes the new HCALL interface and how it
used by KVM.
Signed-off-by: Michael Neuling
Signed-off-by: Jordan Niethe
---
v2:
- Separated into individual patch
augmented for supporting PAPR nested guests later.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kvm_book3s.h | 68 +++-
arch/powerpc/include/asm/kvm_ppc.h | 48 --
arch/powerpc/kvm/book3s.c | 22 +--
arch/powerpc/kvm/book3s_64_mmu_hv.c| 4 +-
arch
Add wrappers for fpr registers to prepare for supporting PAPR nested
guests.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kvm_book3s.h | 31 +++
arch/powerpc/include/asm/kvm_booke.h | 10 +
arch/powerpc/kvm/book3s.c | 16
-...@linux.vnet.ibm.com/
Jordan Niethe (5):
KVM: PPC: Use getters and setters for vcpu register state
KVM: PPC: Add fpr getters and setters
KVM: PPC: Add vr getters and setters
KVM: PPC: Add helper library for Guest State Buffers
KVM: PPC: Add support for nested PAPR guests
Michael Neuling (1
of elements and parsing buffers. This will be used
later by the PAPR nested guest support.
Signed-off-by: Jordan Niethe
---
v2:
- Add missing #ifdef CONFIG_VSXs
- Move files from lib/ to kvm/
- Guard compilation on CONFIG_KVM_BOOK3S_HV_POSSIBLE
- Use kunit for guest state buffer tests
-
Add wrappers for vr registers to prepare for supporting PAPR nested
guests.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kvm_book3s.h | 20 +++
arch/powerpc/kvm/powerpc.c| 50 +--
2 files changed, 45 insertions(+), 25 deletions(-)
diff
. This existing API is still supported.
Signed-off-by: Jordan Niethe
---
Documentation/powerpc/index.rst | 1 +
Documentation/powerpc/kvm-nested.rst | 636
arch/powerpc/include/asm/guest-state-buffer.h | 150 ++-
arch/powerpc/include/asm/hvcall.h
of elements and parsing buffers. This will be used
later by the PAPR nested guest support.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/guest-state-buffer.h | 1001 +
arch/powerpc/lib/Makefile |3 +-
arch/powerpc/lib/guest-state-buffer.c
Add wrappers for vr registers to prepare for supporting PAPR nested
guests.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kvm_book3s.h | 20 +++
arch/powerpc/kvm/powerpc.c| 50 +--
2 files changed, 45 insertions(+), 25 deletions(-)
diff
Add wrappers for fpr registers to prepare for supporting PAPR nested
guests.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kvm_book3s.h | 31 +++
arch/powerpc/include/asm/kvm_booke.h | 10 +
arch/powerpc/kvm/book3s.c | 16
augmented for supporting PAPR nested guests later.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kvm_book3s.h | 68 +++-
arch/powerpc/include/asm/kvm_ppc.h | 48 --
arch/powerpc/kvm/book3s.c | 22 +--
arch/powerpc/kvm/book3s_64_mmu_hv.c| 4 +-
arch
, Shivaprasad
Bhat, Harsh Prateek Bora, Paul Mackerras and Nicholas Piggin.
Jordan Niethe (5):
KVM: PPC: Use getters and setters for vcpu register state
KVM: PPC: Add fpr getters and setters
KVM: PPC: Add vr getters and setters
powerpc: Add helper library for Guest State Buffers
KVM: PPC: Add
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Finding the owner or a queued waiter on a lock with a preempted vcpu
> is indicative of an oversubscribed guest causing the lock to get into
> trouble. Provide some options to detect this situation and have new
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Provide an option that holds off queueing indefinitely while the lock
> owner is preempted. This could reduce queueing latencies for very
> overcommitted vcpu situations.
>
> This is disabled by default.
> ---
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Allow for a reduction in the number of times a CPU from a different
> node than the owner can attempt to steal the lock before queueing.
> This could bias the transfer behaviour of the lock across the
> machine
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Use the spin_begin/spin_cpu_relax/spin_end APIs in qspinlock, which helps
> to prevent threads issuing a lot of expensive priority nops which may not
> have much effect due to immediately executing low then med
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> This gives trylock slightly more strength, and it also gives most
> of the benefit of passing 'val' back through the slowpath without
> the complexity.
> ---
> arch/powerpc/include/asm/qspinlock.h | 39 +++
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> After the head of the queue acquires the lock, it releases the
> next waiter in the queue to become the new head. Add an option
> to prod the new head if its vCPU was preempted. This may only
> have an effect i
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Having all CPUs poll the lock word for the owner CPU that should be
> yielded to defeats most of the purpose of using MCS queueing for
> scalability. Yet it may be desirable for queued waiters to to yield
> to
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> If the head of queue is preventing stealing but it finds the owner vCPU
> is preempted, it will yield its cycles to the owner which could cause it
> to become preempted. Add an option to re-allow stealers befor
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Queued waiters which are not at the head of the queue don't spin on
> the lock word but their qnode lock word, waiting for the previous queued
> CPU to release them. Add an option which allows these waiters to
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Waiters spinning on the lock word should yield to the lock owner if the
> vCPU is preempted. This improves performance when the hypervisor has
> oversubscribed physical CPUs.
> ---
> arch/powerpc/lib/qspinlo
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Store the owner CPU number in the lock word so it may be yielded to,
> as powerpc's paravirtualised simple spinlocks do.
> ---
> arch/powerpc/include/asm/qspinlock.h | 8 +++-
> arch/powerpc/include
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Give the queue head the ability to stop stealers. After a number of
> spins without sucessfully acquiring the lock, the queue head employs
> this, which will assure it is the next owner.
> ---
> arch/powerpc/i
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> Allow new waiters a number of spins on the lock word before queueing,
> which particularly helps paravirt performance when physical CPUs are
> oversubscribed.
> ---
> arch/powerpc/lib/qspinlock.c | 152 +++
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> This uses more optimal ll/sc style access patterns (rather than
> cmpxchg), and also sets the EH=1 lock hint on those operations
> which acquire ownership of the lock.
> ---
> arch/powerpc/include/asm/qspinloc
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
> The first 16 bits of the lock are only modified by the owner, and other
> modifications always use atomic operations on the entire 32 bits, so
> unlocks can use plain stores on the 16 bits. This is the same kin
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
[resend as utf-8, not utf-7]
>
> +/*
> + * Bitfields in the atomic value:
> + *
> + * 0: locked bit
> + * 16-31: tail cpu (+1)
> + */
> +#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
> +
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> -#define queued_spin_lock queued_spin_lock
>
> -static inline void queued_spin_unlock(struct qspinlock *lock)
> +static __always_inline int queued_spin_trylock(struct qspinlock *lock)
> {
> - if (!IS_ENABLED(CONFIG_PARAVIRT_SPINLOC
On Wed, 2022-08-24 at 22:04 +1000, Michael Ellerman wrote:
> Jordan Niethe writes:
> > On Tue, 2022-08-23 at 21:59 +1000, Michael Ellerman wrote:
> > > The semi-recent changes to MSR handling when entering RTAS (firmware)
> > > cause crashes on IBM Cell
R_ME | MSR_RI)
> + insrdi r6, r0, 1, 63 - MSR_HV_LG
Or in non-mnemonic form...
rldimi r6, r0, MSR_HV_LG, 63 - MSR_HV_LG
It is ok to use r0 as a scratch register as it is loaded with 0 afterwards
anyway.
>
> li r0,0
> mtmsrd r0,1/* disable RI before using SRR0/1 */
Reviewed-by: Jordan Niethe
On Wed, 2022-08-17 at 15:06 +1000, Russell Currey wrote:
> From: Nicholas Miehlbradt
>
> This selftest is designed to cover execute-only protections
> on the Radix MMU but will also work with Hash.
>
> The tests are based on those found in pkey_exec_test with modifications
> to use the generic m
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Finding the owner or a queued waiter on a lock with a preempted vcpu
> is indicative of an oversubscribed guest causing the lock to get into
> trouble. Provide some options to detect this situation and have new
> CPUs avoid queueing for a
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Provide an option that holds off queueing indefinitely while the lock
> owner is preempted. This could reduce queueing latencies for very
> overcommitted vcpu situations.
>
> This is disabled by default.
> ---
> arch/powerpc/lib/qspinloc
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Allow for a reduction in the number of times a CPU from a different
> node than the owner can attempt to steal the lock before queueing.
> This could bias the transfer behaviour of the lock across the
> machine and reduce NUMA crossings.
>
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Use the spin_begin/spin_cpu_relax/spin_end APIs in qspinlock, which helps
> to prevent threads issuing a lot of expensive priority nops which may not
> have much effect due to immediately executing low then medium priority.
Just a general
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> This gives trylock slightly more strength, and it also gives most
> of the benefit of passing 'val' back through the slowpath without
> the complexity.
> ---
> arch/powerpc/include/asm/qspinlock.h | 39 +++-
> arch
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> After the head of the queue acquires the lock, it releases the
> next waiter in the queue to become the new head. Add an option
> to prod the new head if its vCPU was preempted. This may only
> have an effect if queue waiters are yielding.
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Having all CPUs poll the lock word for the owner CPU that should be
> yielded to defeats most of the purpose of using MCS queueing for
> scalability. Yet it may be desirable for queued waiters to to yield
> to a preempted owner.
>
> s390
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> If the head of queue is preventing stealing but it finds the owner vCPU
> is preempted, it will yield its cycles to the owner which could cause it
> to become preempted. Add an option to re-allow stealers before yielding,
> and disallow th
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Queued waiters which are not at the head of the queue don't spin on
> the lock word but their qnode lock word, waiting for the previous queued
> CPU to release them. Add an option which allows these waiters to yield
> to the previous CPU i
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Waiters spinning on the lock word should yield to the lock owner if the
> vCPU is preempted. This improves performance when the hypervisor has
> oversubscribed physical CPUs.
> ---
> arch/powerpc/lib/qspinlock.c | 97
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Store the owner CPU number in the lock word so it may be yielded to,
> as powerpc's paravirtualised simple spinlocks do.
> ---
> arch/powerpc/include/asm/qspinlock.h | 8 +++-
> arch/powerpc/include/asm/qspinlock_types.h | 10 +
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Give the queue head the ability to stop stealers. After a number of
> spins without sucessfully acquiring the lock, the queue head employs
> this, which will assure it is the next owner.
> ---
> arch/powerpc/include/asm/qspinlock_types.h
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> Allow new waiters a number of spins on the lock word before queueing,
> which particularly helps paravirt performance when physical CPUs are
> oversubscribed.
> ---
> arch/powerpc/lib/qspinlock.c | 152 ---
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> This uses more optimal ll/sc style access patterns (rather than
> cmpxchg), and also sets the EH=1 lock hint on those operations
> which acquire ownership of the lock.
> ---
> arch/powerpc/include/asm/qspinlock.h | 25 +--
> arc
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> The first 16 bits of the lock are only modified by the owner, and other
> modifications always use atomic operations on the entire 32 bits, so
> unlocks can use plain stores on the 16 bits. This is the same kind of
> optimisation done by c
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
>
> +/*
> + * Bitfields in the atomic value:
> + *
> + * 0: locked bit
> + * 16-31: tail cpu (+1)
> + */
> +#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
> + << _Q_ ## typ
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote:
> -#define queued_spin_lock queued_spin_lock
>
> -static inline void queued_spin_unlock(struct qspinlock *lock)
> +static __always_inline int queued_spin_trylock(struct qspinlock *lock)
> {
> - if (!IS_ENABLED(CONFIG_PARAVIRT_SPINLOC
On Thu, Jun 2, 2022 at 6:49 PM Segher Boessenkool
wrote:
>
> On Thu, Jun 02, 2022 at 01:01:04PM +1000, Jordan Niethe wrote:
> > > What about the more fundamental thing? Have the order of the two halves
> > > of a prefixed insn as ulong not depend on endianness? It rea
On Thu, Jun 2, 2022 at 2:22 AM Segher Boessenkool
wrote:
>
> On Wed, Jun 01, 2022 at 08:43:01PM +1000, Michael Ellerman wrote:
> > Segher Boessenkool writes:
> > > Hi!
> > >
> > > On Tue, May 31, 2022 at 04:59:36PM +1000, Michael Ellerman wrote:
> > >> More problematically it doesn't compile at a
On Sat, Mar 12, 2022 at 6:30 PM Christophe Leroy
wrote:
>
> Hi Jordan
>
> Le 10/11/2021 à 01:37, Jordan Niethe a écrit :
> > From: "Christopher M. Riedl"
> >
> > Rework code-patching with STRICT_KERNEL_RWX to prepare for a later patch
> > which uses
On Wed, Feb 23, 2022 at 1:34 AM Christophe Leroy
wrote:
>
>
>
> Le 02/06/2020 à 07:27, Jordan Niethe a écrit :
> > Currently prefixed instructions are treated as two word instructions by
> > show_user_instructions(), treat them as a single instruction. '<&#x
t;x86/alternatives: Use temporary mm for text poking")
Signed-off-by: Christopher M. Riedl
Signed-off-by: Jordan Niethe
---
v7: - Change to patch_instruction_mm() instead of map_patch_mm() and
unmap_patch_mm()
- include ptesync
---
arch/powerpc/lib/code-patching.c | 106 +++
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