Acked-by: Ian Munsie
Excerpts from andrew.donnellan's message of 2017-06-28 17:22:30 +1000:
> As Ian's stepping down from his maintainer role now that he's leaving IBM,
> Frederic has asked me to add myself to the cxl maintainer list. Updating
> accordingly.
>
>
From: Ian Munsie
I am no longer employed by IBM and will no longer have access to cxl
hardware, so remove myself as a cxl maintainer.
If anyone needs to contact me in the future, please use my personal
email address darkstarsw...@gmail.com
Signed-off-by: Ian Munsie
Cc: Frederic Barrat
Cc
Acked-by: Ian Munsie
Acked-by: Ian Munsie
Looks like a reasonable solution
> Pradipta found this while doing testing for cxlflash. I've tested this
> patch and I'm satisfied that it solves the issue, but I've asked Pradipta
> to test it a bit further.
:)
Acked-by: Ian Munsie
Excerpts from andrew.donnellan's message of 2016-11-23 18:06:59 +1100:
> On 23/11/16 17:49, Ian Munsie wrote:
> > Most of these look fine
> >
> >> -return debugfs_create_file(name, mode, parent, (void __force *)value,
> >> &fops_io_x64);
> >>
Most of these look fine
> -return debugfs_create_file(name, mode, parent, (void __force *)value,
> &fops_io_x64);
> +return debugfs_create_file_unsafe(name, mode, parent,
> + (void __force *)value, &fops_io_x64);
Just wondering what this one is about?
Cheers,
-Ian
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Acked-by: Ian Munsie
Reviewed-by: Ian Munsie
Acked-by: Ian Munsie
Acked-by: Ian Munsie
Acked-by: Ian Munsie
Whoops!
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From: Ian Munsie
pnv_cxl_enable_phb_kernel_api() grabs a reference to the cxl module to
prevent it from being unloaded after the PHB has been switched to CX4 mode.
This breaks the build when CONFIG_MODULES=n as module_mutex doesn't exist.
However, if we don't have modules, we don
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, CONFIG_CXL_BIMODAL, with a dependency on
the pnv_php driver.
Refactor existing code that touches the mode control register in the
regular single mode case into a new function, setup_cxl_protocol_area().
Co-authored-by: Ian Munsie
Cc: Gavin Shan
Signed-off-by: Andrew Donnellan
Signed-off-by: Ian Munsie
igned-off-by: Ian Munsie
Acked-by: Gavin Shan
---
drivers/pci/hotplug/pnv_php.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c
index 2d2f704..e6245b0 100644
--- a/drivers/pci/hotplug/pnv_php.c
+++ b/drivers/pci/ho
definition of struct pnv_php_slot, to asm/pnv-pci.h.
Cc: Gavin Shan
Cc: linux-...@vger.kernel.org
Cc: Bjorn Helgaas
Signed-off-by: Andrew Donnellan
Signed-off-by: Ian Munsie
Acked-by: Gavin Shan
---
V1->V2:
- Dropped extraneous "select HOTPLUG_PCI_POWERNV_BASE" in Kconfig,
From: Ian Munsie
The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
interrupts are routed from the networking hardware to the XSL using the
MSIX table, and from there will be transformed back into an MSIX
interrupt using the cxl style interrupts (i.e. using IVTE entries and
ranges
From: Ian Munsie
The CX4 card cannot cope with a context with PE=0 due to a hardware
limitation, resulting in:
[ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939
[ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborting
Since the kernel API allocates a
From: Ian Munsie
The Mellanox CX4 has a hardware limitation where only 4 bits of the
AFU interrupt number can be passed to the XSL when sending an interrupt,
limiting it to only 15 interrupts per context (AFU interrupt number 0 is
invalid).
In order to overcome this, we will allocate additional
From: Ian Munsie
These APIs will be used by the Mellanox CX4 support. While they function
standalone to configure existing behaviour, their primary purpose is to
allow the Mellanox driver to inform the cxl driver of a hardware
limitation, which will be used in a future patch.
Signed-off-by: Ian
From: Ian Munsie
This hooks up support for using the kernel API with a real PHB. After
the AFU initialisation has completed it calls into the PHB code to pass
it the AFU that will be used by other peer physical functions on the
adapter.
The cxl_pci_to_afu API is extended to work with peer PCI
From: Ian Munsie
This adds support for the peer model of the cxl kernel api to the
PowerNV PHB, in which physical function 0 represents the cxl function on
the card (an XSL in the case of the CX4), which other physical functions
will use for memory access and interrupt services. It is referred
From: Ian Munsie
The vPHB model of the cxl kernel API is a hierarchy where the AFU is
represented by the vPHB, and it's AFU configuration records are exposed
as functions under that vPHB. If there are no AFU configuration records
we will create a vPHB with nothing under it, which is a was
From: Ian Munsie
The cxl kernel API has a concept of a default context associated with
each PCI device under the virtual PHB. The Mellanox CX4 will also use
the cxl kernel API, but it does not use a virtual PHB - rather, the AFU
appears as a physical function as a peer to the networking
From: Ian Munsie
Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus
master to be enabled in order for the CAPI traffic to flow. This should
be harmless to enable for other cxl devices, so unconditionally enable
it in the adapter init flow.
Signed-off-by: Ian Munsie
Reviewed
From: Ian Munsie
The Mellanox CX4 uses a model where the AFU is one physical function of
the device, and is used by other peer physical functions of the same
device. This will require those other devices to grab a reference on the
AFU when they are initialised to make sure that it does not go
From: Ian Munsie
This extends the check that the adapter is in a CAPI capable slot so
that it may be called by external users in the kernel API. This will be
used by the upcoming Mellanox CX4 support, which needs to know ahead of
time if the card can be switched to cxl mode so that it can leave
From: Ian Munsie
The support for using the Mellanox CX4 in cxl mode will require
additions to the PHB code. In preparation for this, move the existing
cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things
more organised.
Signed-off-by: Ian Munsie
Reviewed-by: Andrew
an for pointing it out (Patch 13)
- Added new error label for error paths calling pci_dev_put() -
suggested by Ian Munsie (Patch 15)
- Added newline at end of Kconfig (Patch 15)
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Excerpts from andrew.donnellan's message of 2016-07-13 15:52:45 +1000:
> > +bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct
> > cxl_afu *afu)
>
> If we're sharing these functions between the vPHB and peer models, do we
> have a better place than vphb.c for them?
Sure, I migh
Excerpts from andrew.donnellan's message of 2016-07-12 20:39:13 +1000:
> Some comments below - with those addressed:
>
> Reviewed-by: Andrew Donnellan
Thanks for the review :)
> > V1->V2:
> > - Add an explanation of the peer model to the commit message,
> > and a comment above the pnv
, CONFIG_CXL_BIMODAL, with a dependency on
the pnv_php driver.
Refactor existing code that touches the mode control register in the
regular single mode case into a new function, setup_cxl_protocol_area().
Co-authored-by: Ian Munsie
Cc: Gavin Shan
Signed-off-by: Andrew Donnellan
Signed-off-by: Ian Munsie
igned-off-by: Ian Munsie
Acked-by: Gavin Shan
---
drivers/pci/hotplug/pnv_php.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c
index 2d2f704..e6245b0 100644
--- a/drivers/pci/hotplug/pnv_php.c
+++ b/drivers/pci/ho
From: Ian Munsie
The Mellanox CX4 has a hardware limitation where only 4 bits of the
AFU interrupt number can be passed to the XSL when sending an interrupt,
limiting it to only 15 interrupts per context (AFU interrupt number 0 is
invalid).
In order to overcome this, we will allocate additional
From: Ian Munsie
This hooks up support for using the kernel API with a real PHB. After
the AFU initialisation has completed it calls into the PHB code to pass
it the AFU that will be used by other peer physical functions on the
adapter.
The cxl_pci_to_afu API is extended to work with peer PCI
definition of struct pnv_php_slot, to asm/pnv-pci.h.
Cc: Gavin Shan
Cc: linux-...@vger.kernel.org
Cc: Bjorn Helgaas
Signed-off-by: Andrew Donnellan
Signed-off-by: Ian Munsie
Acked-by: Gavin Shan
---
V1->V2:
- Dropped extraneous "select HOTPLUG_PCI_POWERNV_BASE" in Kconfig,
From: Ian Munsie
The CX4 card cannot cope with a context with PE=0 due to a hardware
limitation, resulting in:
[ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939
[ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborting
Since the kernel API allocates a
From: Ian Munsie
The cxl kernel API has a concept of a default context associated with
each PCI device under the virtual PHB. The Mellanox CX4 will also use
the cxl kernel API, but it does not use a virtual PHB - rather, the AFU
appears as a physical function as a peer to the networking
From: Ian Munsie
The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
interrupts are routed from the networking hardware to the XSL using the
MSIX table, and from there will be transformed back into an MSIX
interrupt using the cxl style interrupts (i.e. using IVTE entries and
ranges
From: Ian Munsie
These APIs will be used by the Mellanox CX4 support. While they function
standalone to configure existing behaviour, their primary purpose is to
allow the Mellanox driver to inform the cxl driver of a hardware
limitation, which will be used in a future patch.
Signed-off-by: Ian
From: Ian Munsie
This adds support for the peer model of the cxl kernel api to the
PowerNV PHB, in which physical function 0 represents the cxl function on
the card (an XSL in the case of the CX4), which other physical functions
will use for memory access and interrupt services. It is referred
From: Ian Munsie
The vPHB model of the cxl kernel API is a hierarchy where the AFU is
represented by the vPHB, and it's AFU configuration records are exposed
as functions under that vPHB. If there are no AFU configuration records
we will create a vPHB with nothing under it, which is a was
sion. Thanks to Gavin Shan for pointing it out (Patch 13)
- Added new error label for error paths calling pci_dev_put() -
suggested by Ian Munsie (Patch 15)
- Added newline at end of Kconfig (Patch 15)
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From: Ian Munsie
The Mellanox CX4 uses a model where the AFU is one physical function of
the device, and is used by other peer physical functions of the same
device. This will require those other devices to grab a reference on the
AFU when they are initialised to make sure that it does not go
From: Ian Munsie
Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus
master to be enabled in order for the CAPI traffic to flow. This should
be harmless to enable for other cxl devices, so unconditionally enable
it in the adapter init flow.
Signed-off-by: Ian Munsie
Reviewed
From: Ian Munsie
This extends the check that the adapter is in a CAPI capable slot so
that it may be called by external users in the kernel API. This will be
used by the upcoming Mellanox CX4 support, which needs to know ahead of
time if the card can be switched to cxl mode so that it can leave
From: Ian Munsie
The support for using the Mellanox CX4 in cxl mode will require
additions to the PHB code. In preparation for this, move the existing
cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things
more organised.
Signed-off-by: Ian Munsie
Reviewed-by: Andrew
Excerpts from andrew.donnellan's message of 2016-07-07 18:15:06 +1000:
> On 07/07/16 16:44, Andrew Donnellan wrote:
> > We can match the vendor, device ID *and* class code - unfortunately
> > there isn't a macro for this, which makes it a little bit less
> > aesthetically pleasing, but I'm pretty s
Excerpts from Frederic Barrat's message of 2016-07-06 20:30:41 +0200:
>
> > @@ -1572,6 +1575,9 @@ static pci_ers_result_t cxl_pci_error_detected(struct
> > pci_dev *pdev,
> >*/
> > for (i = 0; i < adapter->slices; i++) {
> > afu = adapter->afu[i];
> > +
Excerpts from Frederic Barrat's message of 2016-07-06 19:38:18 +0200:
>
> > +/* No special handling for cxl function: */
> > +if (PCI_FUNC(dev->devfn) == 0)
> > +return true;
>
> I believe that is the first time we're getting a hint of the black magic
> which is going to occur wh
Excerpts from andrew.donnellan's message of 2016-07-07 11:18:37 +1000:
> > This is to balance the 'get' done in cxl_check_and_switch_mode(), right?
> > A comment wouldn't hurt. I think we're missing the 'put' on the first
> > error path above (!bridge).
>
> Yep, it's to balance the pci_dev_get() i
Excerpts from Frederic Barrat's message of 2016-07-06 20:41:42 +0200:
> I think we want:
> if (WARN_ON(hwirq <= 0))
> cxl_find_afu_irq() returns 0 if doesn't find the irq, which is not
> supposed to happen here.
Good catch - will fix in v2.
Cheers,
-Ian
_
Excerpts from Frederic Barrat's message of 2016-07-06 20:11:48 +0200:
>
> Le 04/07/2016 15:22, Ian Munsie a écrit :
> > From: Ian Munsie
> >
> > These APIs will be used by the Mellanox CX4 support. While they function
> > standalone to configure existing beh
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I agree with Mikey - this needs a description. But otherwise it looks
good to me, and I'll be happy if it stops any more AFU developers from
reporting their bugs to us, so happy to add this now:
Acked-by: Ian Munsie
Excerpts from Philippe Bergheaud's message of 2016-07-04 17:0
From: Ian Munsie
The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
interrupts are routed from the networking hardware to the XSL using the
MSIX table, and from there will be transformed back into an MSIX
interrupt using the cxl style interrupts (i.e. using IVTE entries and
ranges
From: Ian Munsie
The Mellanox CX4 uses a model where the AFU is one physical function of
the device, and is used by other peer physical functions of the same
device. This will require those other devices to grab a reference on the
AFU when they are initialised to make sure that it does not go
From: Ian Munsie
This extends the check that the adapter is in a CAPI capable slot so
that it may be called by external users in the kernel API. This will be
used by the upcoming Mellanox CX4 support, which needs to know ahead of
time if the card can be switched to cxl mode so that it can leave
, CONFIG_CXL_BIMODAL, with a dependency on
the pnv_php driver.
Refactor existing code that touches the mode control register in the
regular single mode case into a new function, setup_cxl_protocol_area().
Co-authored-by: Ian Munsie
Cc: Gavin Shan
Signed-off-by: Andrew Donnellan
Reviewed-by: Gavin Shan
From: Andrew Donnellan
When calling pnv_php_set_slot_power_state() with state ==
OPAL_PCI_SLOT_OFFLINE, remove devices from the device tree as if we're
dealing with OPAL_PCI_SLOT_POWER_OFF.
Cc: Gavin Shan
Cc: linux-...@vger.kernel.org
Cc: Bjorn Helgaas
Signed-off-by: Andrew Donnellan
Acked-by
From: Andrew Donnellan
The cxl driver will use infrastructure from pnv_php to handle device tree
updates when switching bi-modal CAPI cards into CAPI mode.
To enable this, export pnv_php_find_slot() and
pnv_php_set_slot_power_state(), and add corresponding declarations, as well
as the definition
From: Ian Munsie
The CX4 card cannot cope with a context with PE=0 due to a hardware
limitation, resulting in:
[ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939
[ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborting
Since the kernel API allocates a
From: Ian Munsie
The Mellanox CX4 has a hardware limitation where only 4 bits of the
AFU interrupt number can be passed to the XSL when sending an interrupt,
limiting it to only 15 interrupts per context (AFU interrupt number 0 is
invalid).
In order to overcome this, we will allocate additional
From: Ian Munsie
These APIs will be used by the Mellanox CX4 support. While they function
standalone to configure existing behaviour, their primary purpose is to
allow the Mellanox driver to inform the cxl driver of a hardware
limitation, which will be used in a future patch.
Signed-off-by: Ian
From: Ian Munsie
This hooks up support for using the kernel API with a real PHB. After
the AFU initialisation has completed it calls into the PHB code to pass
it the AFU that will be used by other peer physical functions on the
adapter.
The cxl_pci_to_afu API is extended to work with peer PCI
From: Ian Munsie
This adds support for the peer model of the cxl kernel api to the
PowerNV PHB, and exports APIs to enable the mode, check if a PCI device
is attached to a PHB in this mode, and to set and get the peer AFU for
this mode.
The cxl driver will enable this mode for supported cards
From: Ian Munsie
The cxl kernel API has a concept of a default context associated with
each PCI device under the virtual PHB. The Mellanox CX4 will also use
the cxl kernel API, but it does not use a virtual PHB - rather, the AFU
appears as a physical function as a peer to the networking
From: Ian Munsie
Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus
master to be enabled in order for the CAPI traffic to flow. This should
be harmless to enable for other cxl devices, so unconditionally enable
it in the adapter init flow.
Signed-off-by: Ian Munsie
From: Ian Munsie
The support for using the Mellanox CX4 in cxl mode will require
additions to the PHB code. In preparation for this, move the existing
cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things
more organised.
Signed-off-by: Ian Munsie
---
arch/powerpc/platforms
This series adds support for the Mellanox CX4 network adapter operating in cxl
mode to the cxl driver and the PowerNV PHB code. The Mellanox developers will
submit a separate patch series that makes use of this in the mlx5 driver.
The CX4 card can operate in either pci mode, or cxl mode. In cxl mo
Acked-by: Ian Munsie
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From: Ian Munsie
The commit "powerpc/fadump: trivial fix of spelling mistake, clean up
message" removed a semicolon causing the following compile failure:
arch/powerpc/kernel/fadump.c: In function ‘fadump_invalidate_dump’:
arch/powerpc/kernel/fadump.c:1014:2: error: expected
Thanks Philippe - this looks like a decent solution to the problem (and
I intend to use this for the upcoming cx4 support as well).
Acked-by: Ian Munsie
Excerpts from Philippe Bergheaud's message of 2016-06-30 13:45:37 +0200:
> One should not attempt to switch a PHB into CAPI mode if
From: Ian Munsie
The AFU disable operation has a bug where it will not clear the enable
bit and therefore will have no effect. To date this has likely been
masked by fact that we perform an AFU reset before the disable, which
also has the effect of clearing the enable bit, making the following
Excerpts from Frederic Barrat's message of 2016-06-30 17:50:00 +0200:
>
> Le 30/06/2016 17:32, Ian Munsie a écrit :
> >> For dedicated mode, the CAIA recommends an explicit reset of the AFU
> >> >(section 2.1.1).
> > True, I had forgotten that procedure was a
Excerpts from Frederic Barrat's message of 2016-06-30 16:19:54 +0200:
> I'm not a big fan of the new "clear" argument, which forces us to pass
> an extra 0 most of the time. Why not always clearing the "action" bits
> of the register before applying the command? They are mutually
> exclusive, so
Excerpts from andrew.donnellan's message of 2016-06-30 15:15:02 +1000:
> On 30/06/16 15:00, Michael Ellerman wrote:
> > On Thu, 2016-06-30 at 08:28 +1000, Andrew Donnellan wrote:
> >> On 30/06/16 04:55, Ian Munsie wrote:
> >>>
> >>> From: Ian Munsie
From: Ian Munsie
If a kernel context is initialised and does not have any AFU interrupts
allocated it will cause a NULL pointer dereference when the context is
detached since the irq_names list will not have been initialised.
Move the initialisation of the irq_names list into the
From: Ian Munsie
An issue was noted in our debug logs where the XSL would leave the RA
bit asserted after an AFU reset operation, which would effectively
prevent further AFU reset operations from working.
Workaround the issue by clearing the RA bit with an MMIO write if it is
still asserted
From: Ian Munsie
The AFU disable operation has a bug where it will not clear the enable
bit and therefore will have no effect. To date this has likely been
masked by fact that we perform an AFU reset before the disable, which
also has the effect of clearing the enable bit, making the following
From: Ian Munsie
The Scheduled Process Area is allocated dynamically with enough pages to
fit at least as many processes as the AFU descriptor indicated. Since
the calculation is non-trivial, it does this by calculating how many
processes could fit in an allocation of a given order, and
From: Ian Munsie
If the AFU descriptor of an AFU directed AFU indicates that it supports
0 maximum processes, we will accept that value and attempt to use it.
The SPA will still be allocated (with 2 pages due to another minor bug
and room for 958 processes), and when a context is allocated we
Excerpts from Vaibhav Jain's message of 2016-06-20 14:20:16 +0530:
> > +int cxl_unset_driver_ops(struct cxl_context *ctx)
> > +{
> > +if (atomic_read(&ctx->afu_driver_events))
> > +return -EBUSY;
> > +
> > +ctx->afu_driver_ops = NULL;
> Need a write memory barrier so that afu_driver
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This could probably use a description in the commit message, perhaps
including output showing the before/after difference this makes to
lsvpd, but otherwise it looks fine to me.
@Mikey - this look OK to you?
Acked-by: Ian Munsie
Excerpts from Frederic Barrat's message of 2016-06-15 16:
From: Ian Munsie
This adds support for using CAPP DMA mode, which is required for XSL
based cards such as the Mellanox CX4 to function.
This is currently an RFC as it depends on the corresponding support to
be merged into skiboot first, which was submitted here:
http://patchwork.ozlabs.org
ses a special DMA cxl mode, which uses a slightly
different init sequence for the CAPP and PHB. The kernel support for
this will be in a future patch once the corresponding support has been
merged into skiboot.
Co-authored-by: Ian Munsie
Signed-off-by: Ian Munsie
---
drivers/misc/cxl/cxl.h
From: Ian Munsie
In the kernel API, it is possible to attempt to allocate AFU interrupts
after already starting a context. Since the process element structure
used by the hardware is only filled out at the time the context is
started, it will not be updated with the interrupt numbers that have
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From: Ian Munsie
cxl devices typically access memory using an MMU in much the same way as
the CPU, and each context includes a state register much like the MSR in
the CPU. Like the CPU, the state register includes a bit to enable
relocation, which we currently always enable.
In some cases, it
Sure thing, that actually simplifies things a great deal. Testing now
and will resend shortly :)
-Ian
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