.org/patch/226036/
>>
>>> -Original Message-
>>> From: Wang Dongsheng-B40534
>>> Sent: Friday, March 08, 2013 3:39 PM
>>> To: Wood Scott-B07421; Gala Kumar-B11780
>>> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
>>> S
On Feb 28, 2013, at 2:46 AM, Ramneek Mehresh wrote:
> Add first usb controller node for qonverge qoriq platforms like
> B4860, etc
>
> Signed-off-by: Ramneek Mehresh
> ---
> Applies on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> (branch next)
>
> arch/powerpc/boot/dts/fsl
On Mar 7, 2013, at 8:57 PM, Chunhe Lan wrote:
> On 03/08/2013 12:30 AM, Gala Kumar-B11780 wrote:
>> On Mar 7, 2013, at 2:05 AM, Chunhe Lan wrote:
>>
>>> This patch fixes timeout problems on t4240's sdhci controller:
>>>
>>> mmc0: Too large
On Mar 8, 2013, at 2:32 AM, Chunhe Lan wrote:
> Adding pcie error interrupt edac support for mpc85xx, p3041, p4080,
> and p5020. The mpc85xx uses the legacy interrupt report mechanism -
> the error interrupts are reported directly to mpic. While, the p3041/
> p4080/p5020 attaches the most of erro
On Mar 7, 2013, at 2:05 AM, Chunhe Lan wrote:
> This patch fixes timeout problems on t4240's sdhci controller:
>
> mmc0: Too large timeout requested for CMD25!
> mmc0: Too large timeout requested for CMD25!
> mmc0: Too large timeout requested for CMD25!
>
> Signed-off-by: Chun
On Feb 19, 2013, at 3:14 AM, Harninder Rai wrote:
> Signed-off-by: Harninder Rai
> ---
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
applied to next
- k
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On Feb 19, 2013, at 3:13 AM, Harninder Rai wrote:
> BSC9131RDB doesn't have SDHC enabled. As a result of this typo,
> the node was not getting disabled from the device tree which was
> leading to linux hang during bootup
>
> Signed-off-by: Harninder Rai
> ---
> arch/powerpc/boot/dts/bsc9131rdb.
On Feb 19, 2013, at 3:14 AM, Harninder Rai wrote:
> BSC913x are heterogeneous platforms having DSP and PowerPC.
> * Lot of new IPs like AIC (Antenna Interface Controller), RF (radio) etc
> * Such IPs are not present in any other 85xx platform
> * Lot of optimizations related to ethernet/ASF (Appl
On Feb 18, 2013, at 6:29 PM, Po Liu wrote:
> This facilitates getting the physical address of the SEC node.
>
> Signed-off-by: Liu po
> ---
> arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
Why are you reposting this, I already applied it
On Jan 17, 2013, at 5:26 PM, Timur Tabi wrote:
> From: Timur Tabi
>
> The Freescale DIU driver was recently updated to not require every DIU
> platform function, so now we can remove the unneeded functions from
> some boards.
>
> Signed-off-by: Timur Tabi
> ---
> arch/powerpc/platforms/512x/m
On Jan 17, 2013, at 4:34 PM, Timur Tabi wrote:
> From: Timur Tabi
>
> The PAMU caches use the LIODNs to determine which cache lines hold the
> entries for the corresponding LIODs. The LIODNs must therefore be
> carefully assigned to avoid cache thrashing -- two active LIODs with
> LIODNs that
On Jan 17, 2013, at 4:34 PM, Timur Tabi wrote:
> From: Timur Tabi
>
> Fix and/or improve the compatible strings of the PCI device tree nodes for
> some Freescale SOCs. This fixes some issues and improves consistency among
> the SOCs.
>
> Specifically:
>
> 1) The P1022 has a v1 PCIe controlle
On Jan 17, 2013, at 4:34 PM, Timur Tabi wrote:
> From: Timur Tabi
>
> The PAMU caches use the LIODNs to determine which cache lines hold the
> entries for the corresponding LIODs. The LIODNs must therefore be
> carefully assigned to avoid cache thrashing -- two active LIODs with
> LIODNs that
On Sep 29, 2012, at 6:44 PM, York Sun wrote:
> ePAPR v1.1 requires the spin table to be in cached memory. So we need
> to change the call argument of ioremap to enable cache and coherence.
> We also flush the cache after writing to spin table to keep it compatible
> with previous cache-inhibit sp
On Sep 27, 2012, at 2:02 PM, Chunhe Lan wrote:
> There are some differences of register offset and definition between
> pci and pcie error management registers. While, some other pci/pcie
> error management registers are nearly the same.
>
> To merge pci and pcie edac code into one, it is easier
On Sep 27, 2012, at 11:09 AM, Scott Wood wrote:
> On 09/27/2012 02:02:03 PM, Chunhe Lan wrote:
>> Original process of call:
>> The mpc85xx_pci_err_probe function completes to been registered
>> and enabled of EDAC PCI err driver at the latter time stage of
>> kernel boot in the mpc
On Sep 14, 2012, at 2:57 PM, Chunhe Lan wrote:
> Signed-off-by: Chunhe Lan
> ---
> arch/powerpc/configs/85xx/p1023rds_defconfig |6 ++
> 1 files changed, 6 insertions(+), 0 deletions(-)
applied to next
- k
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On Aug 10, 2012, at 2:40 PM, Scott Wood wrote:
> On 08/10/2012 12:54 AM, dongsheng.w...@freescale.com wrote:
>> +static const struct of_device_id mpic_timer_ids[] = {
>> +{ .compatible = "open-pic,global-timer", },
>> +{ .compatible = "fsl,global-timer", },
>> +{},
>> +};
>> +
>> +sta
On Aug 10, 2012, at 12:53 AM,
wrote:
> From: Wang Dongsheng
>
> Add a description of the OPEN-PIC global timer in the OPEN-PIC document.
>
> Moidfy mpic-timer document. 1.Add a TFRR register region. This register
> is written by software to report the clocking frequency of the PIC timers.
>
>>> As I explained before, this has to be done globally, not from the
>>> probe function, so we can assign a default primary bus if there
>>> isn't any ISA.
>>> There are bugs in the Linux PPC PCI code relating to not having
>>> any primary bus.
>>>
>>> -Scott
>>
>
Guys,
As v3.6-rc1 is now out we really need to get some of these simpler patches
upstream and accepted NOW. Please provide status updates if the patch is
upstream already let me know.
[P1025RDB] (some major differences between upstream and internal P1025RDB
support)
powerpc/85xx: Add Quicc En
I pulling the p3060qds bit out so drop that change from next patch.
- k
On Sep 15, 2011, at 11:31 AM, "Tabi Timur-B04825" wrote:
> Kumar Gala wrote:
>> What happened to looking at pixis vs ngpixis ?
>
> Doh, I knew I was forgetting something.
>
> --
> Timur Tabi
> Linux kernel developer at
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