020 at my disposal. So I would appreciate
it if somebody with a broader view on this SoCs can up with a usable
solution.
This issue will only propagate if the dts sets the clock-frequency field
for the i2c controller in question is set.
gr
E.
--
Elie De Brauwer
__
On 01/21/11 17:22, Elie De Brauwer wrote:
Hello list,
I have a P2020 processor on a custom board which uses the embedded
fsl-esdhc controller. Hardware-wise this is functional and in u-boot
everything seems to behave (mmc part 0 gives the correct partition table
and ext2ls/fatls are capable of
CIE_LINK and call a pci_rescon_bus() on that bus.
After doing this I can find access the FPGA, and reload it if needed.
Not a clue if this is 'the proper way' to do it, but it works for me.
gr
E.
--
Elie De Brauwer
___
Linuxppc-dev mail
On 01/24/11 10:28, tiejun.chen wrote:
Elie De Brauwer wrote:
On 01/24/11 09:15, tiejun.chen wrote:
Elie De Brauwer wrote:
On 01/24/11 04:26, tiejun.chen wrote:
Elie De Brauwer wrote:
Hello list,
I have a P2020 processor on a custom board which uses the embedded
fsl-esdhc controller
On 01/24/11 09:15, tiejun.chen wrote:
Elie De Brauwer wrote:
On 01/24/11 04:26, tiejun.chen wrote:
Elie De Brauwer wrote:
Hello list,
I have a P2020 processor on a custom board which uses the embedded
fsl-esdhc controller. Hardware-wise this is functional and in u-boot
everything seems to
On 01/24/11 04:26, tiejun.chen wrote:
Elie De Brauwer wrote:
Hello list,
I have a P2020 processor on a custom board which uses the embedded
fsl-esdhc controller. Hardware-wise this is functional and in u-boot
everything seems to behave (mmc part 0 gives the correct partition table
and ext2ls
set:
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_OF=y
CONFIG_MMC_SDHCI_OF_ESDHC=y
any pointers are welcome.
gr
E.
--
Elie De Brauwer
___
Linuxppc
