Re: PPC PCI bus registers

st Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300 Fountain Hills, AZ 85268| web: www.embeddedARM.com ___ Linuxppc-dev mailing list Linuxppc-dev@lists.

Re: PPC PCI bus registers

le to find any. If there are any example drivers or documentation that you know of on this topic I'd be quite interested if you could point me to it. Thanks for your patience and time you've been quite helpful. -- Best Regards, ____

Re: PPC PCI bus registers

t;* ioremap is the standard one and provides non-cacheable guarded mappings * and can be hooked by the platform via ppc_md " Can you verify if my understanding is correct, or let me know if I need to add memory barriers? -- Best Regards, ____

PPC PCI bus registers

true on a custom board I am working on(with an FPGA connected via the PCI bus) and as a result I've added a byte swap command in busybox to accommodate this feature... -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | vo

Re: image/wrapper script questions

e, but if anyone could provide any pointers on how to do this I would really appreciate it. -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300

image/wrapper script questions

st Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300 Fountain Hills, AZ 85268| web: www.embeddedARM.com ___ Linuxppc-dev mailing list Li

Re: FPGA IRQ design question

e FPGA connects and external interrupt to the SoC? Can you point me to a document explaining the interrupt-map-mask and interrupt-map arguments? Thanks for any pointers. -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | voic

FPGA IRQ design question

fpga irq registers. Any comments would be appreciated. -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300 Fountain Hills, AZ

PowerPC iotable_init equivalent?

if (!my_reg) my_reg = (unsigned char *) ioremap(REG_PHYS_BASE, REG_SIZE); //do something with the reg } -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525

Example dts file

so drivers can parse the dts file to know what devices are present. -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300 Fountain Hills,

Re: AMCC 440EP phy detection

er to boot). -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300 Fountain Hills, AZ 85268| web: www.embed

Re: AMCC 440EP phy detection

initialization? On Tue, Apr 7, 2009 at 9:32 AM, Eddie Dawydiuk wrote: Hello, I'm working on a board based on the Yosemite AMCC 440EP eval board. I'm having some difficulty getting both network interfaces working. The first problem I found is the ibm_newemac driver was detecting the two phys at

Re: AMCC 440EP phy detection

was never asserting for Eth0 a quick user space program verified tx enable was configured as a GPIO pin. On Tue, Apr 7, 2009 at 9:32 AM, Eddie Dawydiuk wrote: Hello, I'm working on a board based on the Yosemite AMCC 440EP eval board. I'm having some difficulty getting both network

Re: AMCC 440EP phy detection

e response. I would try the mii command in uboot. It seems like it detected the phys. Try enable the loopbacks at the different stages to see if the traffic is returning. This excerise is much easier in uboot than linux. Feng Kan AMCC Software Eddie Dawydiuk wrote: Hello, I'm working o

AMCC 440EP phy detection

fact that the driver detected a phy at address 0 might be a clue, but I can't make much of the clue. So I thought I'd post this info in the hopes someone else might have run into a similar problem or have a suggestion. -- Best Regards, __

Re: [RFC]PPC driver lock for DMA registers

are some good examples of of_platform drivers to look at: drivers/block/xsysace.c drivers/spi/xilinx_spi.c drivers/i2c/busses/i2c-ibm_iic.c Thanks for the suggestions, and the pointer to some reference drivers ;) -- Best Regards, ____ Ed

[RFC]PPC driver lock for DMA registers

PGA regs. I'd really appreciate any feedback or suggestions. -- Best Regards, ____ Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300 Fountain Hills, AZ 85

Re: [PATCH, RFC]

Hello, >> So if you have any suggestions on >> this approach using the simpleImage please let me know. > > Before I answer this, what bootloader are you using? We are using a custom bootloader we developed ourselves. The bootloader is very minimal as one of our primary design goals is a fast boot

Re: [PATCH, RFC]

Hello, > On a more general note; this patch also diverges from the original > model for simple image. The idea behind simpleimage was that it would > contain a fully formed device tree, with no fixups necessary. I want > to think carefully before diverging from that. I wasn't aware of these des

Re: [PATCH, RFC]

let me know. On another note, can you tell me/point me to some documentation on how to get a unique machine ID for a new board? -- Best Regards, ________  Eddie Dawydiuk, Technologic Systems | voice:  (480) 837-5200  16525 East

Re: [PATCH, RFC]

Hello, Let's try this one more time. The last patch was using the clocks for a custom board based on the Yosemite board and was referencing a non-existent ethNadr( I forgot to pull out this code out). Signed-off-by: Eddie Dawydiuk diff -urN linux-2.6.28.orig/arch/powerpc/boot/simpl

Re: [PATCH, RFC]

eryone will have to edit it. You need > to specify this in your board DTS file or via some other configurable > mechansim. Oops, sorry I forgot to pull out the debug code... Signed-off-by: Eddie Dawydiuk diff -urN linux-2.6.28.orig/arch/powerpc/boot/Makefile linux-2.6.28/arch/powerpc/b

[PATCH, RFC]

platform_ops.fixups = yosemite_fixups; + platform_ops.exit = ibm44x_dbcr_reset; +} -- Best Regards, Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200 16525 East Laser Drive | fax:(480) 837-5300 Fountain Hills, AZ 85268