is a straightforward conversion from calling
> filemap_write_and_wait_range in their fsync operation to calling
> file_write_and_wait_range.
>
> Signed-off-by: Jeff Layton
Acked-by: Dave Kleikamp
(for jfs)
> ---
> arch/powerpc/platforms/cell/spufs/file.c | 2 +-
> drivers/s
On Wed, 2011-03-02 at 14:37 +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2011-02-07 at 19:29 +1100, David Gibson wrote:
> > On Wed, Feb 02, 2011 at 06:00:25PM -0600, Dave Kleikamp wrote:
> > > On Thu, 2011-02-03 at 10:06 +1100, David Gibson wrote:
> > > > On Tue, Fe
Allow the early debug uart address to be overridden from the kernel
command line.
I would have preferred use the uart's virtual-reg property, but the device
tree hasn't been unflatted yet, and I don't know a reliable way to find it.
Signed-off-by: Dave Kleikamp
Cc: Benjamin He
For AMP, different kernel instances load into separate memory regions.
Read the start of memory from the device tree and limit the memory to what's
specified in the device tree.
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
The 44x code (which is shared by 47x) assumes the available physical memory
begins at 0x. This is not necessarily the case in an AMP
environment.
Support CONFIG_RELOCATABLE for 476 in order to allow the kernel to be
loaded into a higher memory range.
Signed-off-by: Dave Kleikamp
Cc
so that it can use information from the device tree.
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/setup_32.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel
These are completely independent OS instances, each running on 2 cores.
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/boot/Makefile|6 ++-
arch/powerpc/boot/dts/iss476-amp1.dts | 119
Since other OS's may be running on the other cores don't use tlbivax
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/include/asm/mmu.h |2 +-
arch/powerpc/kernel/setup_32.c |2 ++
arch/powerpc/mm/tl
ied memory range in boot wrapper
4. Cleaned up the dts files
v2:
1. Replace ugly hack in boot wrapper with generic solution
Dave Kleikamp (6):
powerpc: Move udbg_early_init() after early_init_devtree()
powerpc/44x: allow override to hard-coded uart address
powerpc/47x: allow kernel to be
On Wed, 2011-02-02 at 13:43 +1100, David Gibson wrote:
> On Tue, Feb 01, 2011 at 12:48:46PM -0600, Dave Kleikamp wrote:
> > These are completely independent OS instances, each running on 2
> > cores.
>
> [snip]
> > +/memreserve/ 0x01f0 0x0010;
>
> A comm
On Wed, 2011-02-02 at 01:45 -0600, Kumar Gala wrote:
> On Feb 1, 2011, at 12:48 PM, Dave Kleikamp wrote:
>
> > Signed-off-by: Dave Kleikamp
> > Cc: Benjamin Herrenschmidt
> > Cc: Josh Boyer
> > Cc: linuxppc-dev@lists.ozlabs.org
> > ---
> > arch/power
On Fri, 2011-02-04 at 08:56 -0500, Josh Boyer wrote:
> On Tue, Feb 01, 2011 at 12:48:44PM -0600, Dave Kleikamp wrote:
> >diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
> >index 2a030d8..b33c5e6 100644
> >--- a/arch/powerpc/mm/tlb_nohash.c
>
On Fri, 2011-02-04 at 09:07 -0500, Josh Boyer wrote:
> On Tue, Feb 01, 2011 at 12:48:45PM -0600, Dave Kleikamp wrote:
> >+static ibm4xx_memstart;
> >+
> > static void iss_4xx_fixups(void)
> > {
> >-ibm4xx_sdram_fixup_memsize();
> >+void *memory;
On Thu, 2011-02-03 at 16:03 +1100, David Gibson wrote:
> On Wed, Feb 02, 2011 at 05:53:59PM -0600, Dave Kleikamp wrote:
> > On Thu, 2011-02-03 at 10:08 +1100, David Gibson wrote:
> > > On Tue, Feb 01, 2011 at 12:48:44PM -0600, Dave Kleikamp wrote:
> > > > Since ot
On Thu, 2011-02-03 at 10:06 +1100, David Gibson wrote:
> On Tue, Feb 01, 2011 at 12:48:41PM -0600, Dave Kleikamp wrote:
> > so that it can use information from the device tree.
>
> Hrm. On the other hand this means that the early_init_devtree() code
> can't benefit from ha
On Thu, 2011-02-03 at 10:08 +1100, David Gibson wrote:
> On Tue, Feb 01, 2011 at 12:48:44PM -0600, Dave Kleikamp wrote:
> > Since other OS's may be running on the other cores don't use tlbivax
>
> [snip]
> > +#ifdef CONFIG_44x
> > +void __init early_init_mmu_4
On Wed, 2011-02-02 at 01:48 -0600, Kumar Gala wrote:
> On Feb 1, 2011, at 12:48 PM, Dave Kleikamp wrote:
>
> > Since other OS's may be running on the other cores don't use tlbivax
>
> Are you guys building SMP kernel for use with AMP? Just wondering why you'd
On Tue, 2011-02-01 at 13:13 -0600, Scott Wood wrote:
> On Tue, 1 Feb 2011 12:48:45 -0600
> Dave Kleikamp wrote:
>
> > For AMP, different kernel instances load into separate memory regions.
> > Read the start of memory from the device tree and limit the memory to what&#
Since other OS's may be running on the other cores don't use tlbivax
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/include/asm/mmu.h |2 +-
arch/powerpc/kernel/setup_32.c |2 ++
arch/powerpc/mm/tl
For AMP, different kernel instances load into separate memory regions.
Read the start of memory from the device tree and limit the memory to what's
specified in the device tree.
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
These are completely independent OS instances, each running on 2 cores.
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/boot/Makefile|6 ++-
arch/powerpc/boot/dts/iss476-amp1.dts | 119
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/configs/44x/iss476-smp_defconfig |6 ++--
arch/powerpc/kernel/head_44x.S| 42
so that it can use information from the device tree.
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/setup_32.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel
Allow the early debug uart address to be overridden from the kernel
command line.
I would have preferred use the uart's virtual-reg property, but the device
tree hasn't been unflatted yet, and I don't know a reliable way to find it.
Signed-off-by: Dave Kleikamp
Cc: Benjamin He
These patches add Asynchonous MultiProcessing support for the 47x chipset.
This allows independent OS instances to run on separate cores.
V2:
1. Replace ugly hack in boot wrapper with generic solution
Dave Kleikamp (6):
powerpc: Move udbg_early_init() after early_init_devtree()
powerpc/44x
Signed-off-by: Dave Kleikamp
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/configs/44x/iss476-smp_defconfig |6 ++--
arch/powerpc/kernel/head_44x.S| 42 -
arch/powerpc/mm/44x_mmu.c | 13 ++--
4
Since other OS's may be running on the other cores don't use tlbivax
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/mmu.h |2 +-
arch/powerpc/kernel/setup_32.c |2 ++
arch/powerpc/mm/tlb_nohash.c | 21 -
3 files changed, 23 insertions(+), 2
so that it can use information from the device tree.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/kernel/setup_32.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1d2fbc9..d1ca976 100644
--- a
These are completely independent OS instances, each running on 2 cores.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/boot/Makefile |9 ++-
arch/powerpc/boot/dts/iss476-amp1.dts | 119 ++
arch/powerpc/boot/dts/iss476-amp2.dts | 123
These patches add Asynchonous MultiProcessing support for the 47x chipset.
This allows independent OS instances to run on separate cores.
Dave Kleikamp (5):
powerpc: Move udbg_early_init() after early_init_devtree()
powerpc/44x: allow override to hard-coded uart address
powerpc/47x: allow
Allow the early debug uart address to be overridden from the kernel
command line.
I would have preferred use the uart's virtual-reg property, but the device
tree hasn't been unflatted yet, and I don't know a reliable way to find it.
Signed-off-by: Dave Kleikamp
---
arch
The DD2 core still has some unstability. Define CPU_FTR_476_DD2 to
enable workarounds in later patches.
This is based on an earlier, unreleased patch for DD1 by Ben Herrenschmidt.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/cputable.h |3 ++-
arch/powerpc/kernel/cputable.c
These patches add a workaround to avoid a hang on the DD2 level of the
476FP core. This hardware bug will be fixed in future products, but this
particular core will used in production.
Dave Kleikamp (2):
powerpc/476: define specific cpu table entry DD2 core
powerpc/476: Workaround for PLB6
The 476FP core may hang if an instruction fetch happens during an msync
following a tlbsync. This workaround makes sure that enough instruction
cache lines are pre-fetched before executing the msync. (sync and msync
are the same to the compiler.)
Signed-off-by: Dave Kleikamp
---
arch/powerpc
On Tue, 2010-12-07 at 14:48 +0800, xufeng zhang wrote:
> Hi Dave,
>
> I have a question with the below patch you made before:
>
> powerpc/booke: Add support for advanced debug registers
>
> From: Dave Kleikamp
>
> Based on pa
On Thu, 2010-10-14 at 11:52 +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2010-09-24 at 13:01 -0500, Dave Kleikamp wrote:
> > On PPC_MMU_NOHASH processors that support a large number of contexts,
> > implement a lazy flush_tlb_mm() that switches to a free context, marking
> &
The 476 requires an isync following a write to certain SPRs in order for
their changes to be effective. Such is the case with the DSTI bit, so
the first isync may not be affected by an immediate change to CCR2, but
a second isync instruction will repect the setting.
Signed-off-by: Dave Kleikamp
s where we are switching context.
> In those situations, we explicitly clear the DSTI bit before performing
> isync, and set it again afterward. We also need to do the same when we
> perform isync after explicitly flushing the TLB.
>
> Signed-off-by: Dave Kleikamp
> ---
>
hose situations, we explicitly clear the DSTI bit before performing
isync, and set it again afterward. We also need to do the same when we
perform isync after explicitly flushing the TLB.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/reg_booke.h |4
arch/powerpc/kernel/head_4
On Tue, 2010-09-28 at 07:10 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2010-09-27 at 10:26 -0500, Dave Kleikamp wrote:
> > I think I made it a config option at Ben's request when I first started
> > this work last year, before being sidetracked by other priorities. I
>
On Mon, 2010-09-27 at 11:04 -0400, Josh Boyer wrote:
> On Fri, Sep 24, 2010 at 01:01:36PM -0500, Dave Kleikamp wrote:
> >When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2
> >register, the isync command does not flush the shadow TLB (iTLB & dTLB).
> >
>
which is set during init, dependent upon MMU_FTR_TYPE_47x.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/mm/mmu_context_nohash.c | 154 +++---
arch/powerpc/mm/mmu_decl.h |8 ++
arch/powerpc/mm/tlb_nohash.c | 28 +-
3 files changed, 174
that
the feature works as expected, the option can probably be removed.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/reg_booke.h |4
arch/powerpc/kernel/head_44x.S| 25 +
arch/powerpc/mm/tlb_nohash_low.S | 14 +-
arch/pow
These two patches reduce the frequency that the tlb caches are flushed in
hardware. Both the normal tlb cache and the "shadow" tlb cache, which
separates the tlbs for data and instruction access (dTLB and iTLB).
Dave Kleikamp (2):
476: Set CCR2[DSTI] to prevent isync from flushing
Sorry! Forgot to change the subject.
Shaggy
On Wed, 2010-08-18 at 11:44 -0500, Dave Kleikamp wrote:
> Josh,
> Here are some bug fixes for the powerpc-4xx tree. It'd be nice if they
> could make it into 2.6.46.
>
> Thanks,
> Shaggy
>
> Dave Kleikamp (4):
>
There are two entries for .cpu_user_features in
arch/powerpc/kernel/cputable.c. Remove the one that doesn't belong
Signed-off-by: Dave Kleikamp
---
arch/powerpc/kernel/cputable.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/cputable.c b
The interrupt stacks need to be indexed by the physical cpu since the
critical, debug and machine check handlers use the contents of SPRN_PIR to
index the critirq_ctx, dbgirq_ctx, and mcheckirq_ctx arrays.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/kernel/irq.c | 15
Signed-off-by: Dave Kleikamp
---
arch/powerpc/mm/tlb_nohash_low.S |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index cfa7682..b9d9fed 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc
Josh,
Here are some bug fixes for the powerpc-4xx tree. It'd be nice if they
could make it into 2.6.46.
Thanks,
Shaggy
Dave Kleikamp (4):
powerpc/47x: Make sure mcsr is cleared before enabling machine check
interrupts
powerpc/47x: Remove redundant line from cputable.c
powerp
Clear the machine check syndrom register before enabling machine check
interrupts. The initial state of the tlb can lead to parity errors being
flagged early after a cold boot.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/kernel/head_44x.S |4
1 files changed, 4 insertions(+), 0
Subject: [PATCH] powerpc: fix userspace build of ptrace.h
> >
> > Build of ptrace.h failed for assembly because it
> > pulls in stdint.h.
> > Use exportable types (__u32, __u64) to avoid the dependency
> > on stdint.h.
> >
> > Signed-off-by: Sam
9fa5f870ebf1e
> Date: Mon, 8 Feb 2010 11:51:05 + (11:51 +)
> from: Dave Kleikamp
>
> Signed-off-by: Andrey Volkov
>
> ---
>
> arch/powerpc/include/asm/ptrace.h |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
>
> diff --git a/arch/po
On Wed, 2010-05-05 at 11:11 -0400, Josh Boyer wrote:
> On Fri, Mar 05, 2010 at 01:45:54PM -0700, Dave Kleikamp wrote:
> >+config ISS4xx
> >+bool "ISS 4xx Simulator"
> >+depends on (44x || 40x)
> >+default n
> >+select 405GP if
;PPC47x_MCSR_FPR' undeclared (first
> >use in this function)
> >arch/powerpc/kernel/traps.c:415: error: 'PPC47x_MCSR_IPR' undeclared (first
> >use in this function)
> >make[1]: *** [arch/powerpc/kernel/traps.o] Error 1
> >make: *** [arch/powerpc/kernel]
On Mon, 2010-03-29 at 17:01 +0530, K.Prasad wrote:
> On Fri, Mar 26, 2010 at 04:11:45PM -0500, Dave Kleikamp wrote:
> > On Tue, 2010-03-23 at 19:37 +0530, K.Prasad wrote:
> > > plain text document attachment (ppc64_hbkpt_02)
> > > Implement perf-events based hw-brea
On Tue, 2010-03-23 at 19:37 +0530, K.Prasad wrote:
> plain text document attachment (ppc64_hbkpt_02)
> Implement perf-events based hw-breakpoint interfaces for PPC64 processors.
> These interfaces help arbitrate requests from various users and schedules
> them as appropriate.
>
> Signed-off-by: K.
On Sun, 2010-03-07 at 15:08 -0800, Hollis Blanchard wrote:
> On Fri, Mar 5, 2010 at 12:43 PM, Dave Kleikamp
> wrote:
> >
> > powerpc/476: Add isync after loading mmu and debug spr's
> >
> > From: Dave Kleikamp
> >
> > 476 requires an isync afte
powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |5 +
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c| 14 ++
arch
powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |2 ++
arch/powerpc/kernel/head_44x.S|1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc
powerpc/476: Software workaround to fix dcr read/write sequencing.
From: Dave Kleikamp
Copy the register containing the dcr address to a spr before mfdcrx or
mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use
as a dummy register, as it is only otherwise used by critical
powerpc/476: Add isync to the top of all exception handlers for DD1.1 core
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |7 ++-
arch/powerpc/kernel/head_booke.h |3 ++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff
-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h | 10 +++
arch/powerpc/include/asm/ppc-opcode.h |4 +++
arch/powerpc/include/asm/reg_booke.h |9 +++
arch/powerpc/kernel/entry_32.S| 35 +++---
arch/powerpc/kernel/head_44x.S
core.
Signed-off-by: Torez Smith
Signed-off-by: Dave Kleikamp
---
arch/powerpc/boot/Makefile|5 +
arch/powerpc/boot/dts/iss4xx-mpic.dts | 155 +++
arch/powerpc/boot/dts/iss4xx.dts | 116 +++
arch/powerpc/boot/treeboot-iss
ional workaround that will be addressed
in a separate patch, which may not need to be picked up into the
mainline kernel.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c |
powerpc/47x: defconfig for 476 on the iss 4xx simulator
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/configs/44x/iss476-smp_defconfig | 1026 +
1 files changed, 1026 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/configs/44x/iss476
powerpc/476: Add isync after loading mmu and debug spr's
From: Dave Kleikamp
476 requires an isync after loading MMU and debug related SPR's. Some of
these are in performance-critical paths and may need to be optimized, but
initially, we're playing it safe.
Signed-off-by: Torez
d-off-by: Torez Smith
Signed-off-by: Dave Kleikamp
---
arch/powerpc/kernel/head_booke.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 50504ae..a0bf158 100644
--- a/arch/powerpc/kernel/head_bo
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c |1 +
ar
powerpc/47x: Base ppc476 support
From: Dave Kleikamp
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.
The goal is to have a single binary that will run on 44x and 47x, b
powerpc/44x: break out cpu init code into stand-alone function
From: Dave Kleikamp
The 47x platform supports multiple cores and shares code with 44x.
Break out code that is common for initializing the primary and secondary
cpus into a function which can be called for both.
Signed-off-by: Dave
nt
- fixed PVR values in cputable.c
- replaced re-definition of STACK_FRAME_REGS_MARKER with include of ptrace.h
- removed PPC_44x_46x config option
- Kconfig: ISS4xx shouldn't select 440GP for 47x
- Separate out DD1 workaround from DD1.1 workarounds
--
Dave Kleikamp
IBM Linux Technology Center
__
On Fri, 2010-03-05 at 03:15 -0600, Kumar Gala wrote:
> On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote:
>
> > On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp
> > wrote:
> > powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
> >
&g
On Tue, 2010-03-02 at 08:50 -0600, Kumar Gala wrote:
> On Mar 1, 2010, at 1:13 PM, Dave Kleikamp wrote:
>
> > powerpc/booke: Add Stack Marking support to Booke Exception Prolog
> >
> > From: Torez Smith
> >
> > Signed-off-by: Torez Smit
On Mon, 2010-03-01 at 15:24 -0500, Josh Boyer wrote:
> On Mon, Mar 01, 2010 at 02:13:52PM -0500, Dave Kleikamp wrote:
> >powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
> >
> >From: Benjamin Herrenschmidt
> >
> >There are still some unstabl
On Mon, 2010-03-01 at 15:29 -0500, Josh Boyer wrote:
> On Mon, Mar 01, 2010 at 12:16:00PM -0700, Dave Kleikamp wrote:
> >diff --git a/arch/powerpc/platforms/44x/Kconfig
> >b/arch/powerpc/platforms/44x/Kconfig
> >index 1dfc1c1..915c295 100644
> >--- a/arch/powerpc/pla
On Mon, 2010-03-01 at 15:08 -0600, Olof Johansson wrote:
> On Mon, Mar 01, 2010 at 05:13:23AM -0700, Dave Kleikamp wrote:
> > powerpc/476: add machine check handler for 47x core
> >
> > From: Dave Kleikamp
> >
> > The 47x core's MCSR varies from 4
for any other
> patch).
Right, wanted to make sure they approved of the current state of the
patches. They'll go through Ben anyway.
> On Mon, Mar 01, 2010 at 12:13:15PM -0700, Dave Kleikamp wrote:
> >diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
&g
powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |5 +
arch/powerpc/kernel/head_booke.h |3 +++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a
powerpc/476: Software workaround to fix dcr read/write sequencing.
From: Dave Kleikamp
Copy the register containing the dcr address to a spr before mfdcrx or
mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use
as a dummy register, as it is only otherwise used by critical
powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |2 ++
arch/powerpc/kernel/head_44x.S|1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc
-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h | 10 +++
arch/powerpc/include/asm/ppc-opcode.h |4 +++
arch/powerpc/include/asm/reg_booke.h |9 +++
arch/powerpc/kernel/entry_32.S| 35 +++---
arch/powerpc/kernel/head_44x.S
powerpc/476: Add isync to the top of all exception handlers for DD1.1 core
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |7 ++-
arch/powerpc/kernel/head_booke.h |3 ++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff
tches.
The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1
and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1
defined.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/cputable.h |2 ++
arch/powerpc/kernel/cputable.c |
powerpc/47x: defconfig for 476 on the iss 4xx simulator
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/configs/44x/iss476-smp_defconfig | 1023 +
1 files changed, 1023 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/configs/44x/iss476
powerpc/476: Add isync after loading mmu and debug spr's
From: Dave Kleikamp
476 requires an isync after loading MMU and debug related SPR's. Some of
these are in performance-critical paths and may need to be optimized, but
initially, we're playing it safe.
Signed-off-by
core.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/boot/Makefile|5 +
arch/powerpc/boot/dts/iss4xx-mpic.dts | 155 +++
arch/powerpc/boot/dts/iss4xx.dts | 116 +++
arch/powerpc/boot/treeboot-iss4xx.c | 56 +++
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/include/asm/reg_booke.h |
powerpc/47x: Base ppc476 support
From: Dave Kleikamp
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.
The goal is to have a single binary that will run on 44x and 47x, b
powerpc/booke: Add Stack Marking support to Booke Exception Prolog
From: Torez Smith
Signed-off-by: Torez Smith
Signed-off-by: Dave Kleikamp
---
arch/powerpc/kernel/head_booke.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/head_booke.h b
powerpc/44x: break out cpu init code into stand-alone function
From: Dave Kleikamp
The 47x platform supports multiple cores and shares code with 44x.
Break out code that is common for initializing the primary and secondary
cpus into a function which can be called for both.
Signed-off-by: Dave
t the ISS simulator, and
patches 8-13 add workarounds for DD1 and DD1.1 hardware bugs.
--
Dave Kleikamp
IBM Linux Technology Center
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code to delete the break/watchpoints checks the dac* and
iac* registers for zero to determine if they are enabled. Instead, they
should check the dbcr* bits.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/kernel/ptrace.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions
powerpc/booke: Fix a couple typos in the advanced ptrace code
Found and fixed a couple typos in the advanced ptrace patches.
(These patches are currently in benh's next tree.)
Signed-off-by: Dave Kleikamp
Cc: Benjamin Herrenschmidt
Cc: linuxppc-dev list
---
diff --git a/arch/powerpc/in
powerpc/booke: Add support for advanced debug registers
From: Dave Kleikamp
Based on patches originally written by Torez Smith.
This patch defines context switch and trap related functionality
for BookE specific Debug Registers. It adds support to ptrace()
for setting and getting BookE related
powerpc/booke: Add definitions for advanced debug registers
From: Dave Kleikamp
Based on patches originally written by Torez Smith.
This patch adds additional definitions for BookE Debug Registers
to the reg_booke.h header file.
Signed-off-by: Dave Kleikamp
Acked-by: David Gibson
Cc: Torez
powerpc: Extended ptrace interface
From: Dave Kleikamp
Based on patches originally written by Torez Smith.
Add a new extended ptrace interface so that user-space has a single
interface for powerpc, without having to know the specific layout
of the debug registers.
Implement
powerpc/booke: Introduce new CONFIG options for advanced debug registers
From: Dave Kleikamp
Introduce new config options to simplify the ifdefs pertaining to the
advanced debug registers for booke and 40x processors:
CONFIG_PPC_ADV_DEBUG_REGS - boolean: true for dac-based processors
ion_value = 0;
3. PTRACE_DELHWDEBUG
Takes an integer which identifies an existing breakpoint or watchpoint
(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
corresponding breakpoint or watchpoint..
--
Dave Kleikamp
IBM Linux Technology Center
On Mon, 2010-01-18 at 16:34 -0600, Dave Kleikamp wrote:
> On Thu, 2009-12-10 at 20:23 -0600, Kumar Gala wrote:
> > Is GDB smart enough to deal w/no condition_regs? On some Book-E
> > devices we have 2 IACs, 2 DACs, and 0 DVCs. Does it need to be in the
> > features?
>
&
On Thu, 2009-12-10 at 20:45 -0600, Kumar Gala wrote:
> What do we do in EDM mode? We need a flag somewhere to determine if
> HW supports conveying DBCR0[EDM] and if it does which of the ptrace
> calls fails?
I really don't have a good answer to this. I'm open to any and all
advice.
Shaggy
--
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