On Fri, Jun 18, 2021 at 7:30 AM Stefano Stabellini
wrote:
>
> On Thu, 17 Jun 2021, Claire Chang wrote:
> > Add a new function, swiotlb_init_io_tlb_mem, for the io_tlb_mem struct
> > initialization to make the code reusable.
> >
> > Signed-off-by: Claire Chang
> > Reviewed-by: Christoph Hellwig
>
Reset_link() callback function was called before mmio_enabled() in
pcie_do_recovery() function actually, so rearrange the general
sequence betwen step 2 and step 3 accordingly.
Signed-off-by: Wesley Sheng
---
Documentation/PCI/pci-error-recovery.rst | 23 ---
1 file changed,
On Tue, 1 Jun 2021 14:36:25 +0800, Shaokun Zhang wrote:
> Function 'event_ebb_init' and 'event_leader_ebb_init' are declared
> twice in the header file, so remove the repeated declaration.
Applied to powerpc/next.
[1/1] selftests/powerpc: Remove the repeated declaration
https://git.kernel.o
On Tue, 1 Jun 2021 12:02:00 -0700, t...@redhat.com wrote:
> With gcc 10.3, there is this compiler error
> compiler.h:56:26: error: this statement may
> fall through [-Werror=implicit-fallthrough=]
>
> mpc52xx_gpt.c:586:2: note: here
> 586 | case WDIOC_GETTIMEOUT:
> | ^~~~
>
> [...]
A
On Fri, 28 May 2021 11:27:52 -0700, Nathan Chancellor wrote:
> A change in clang 13 results in the __lwsync macro being defined as
> __builtin_ppc_lwsync, which emits 'lwsync' or 'msync' depending on what
> the target supports. This breaks the build because of -Werror in
> arch/powerpc, along with
On Thu, 10 Jun 2021 17:29:49 +1000, Michael Ellerman wrote:
> When delivering a signal to a sigaction style handler (SA_SIGINFO), we
> pass pointers to the siginfo and ucontext via r4 and r5.
>
> Currently we populate the values in those registers by reading the
> pointers out of the sigframe in u
On Tue, 1 Jun 2021 16:51:27 +0800, Baokun Li wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> arch/powerpc/platforms/cell/spufs/switch.c: In function 'check_ppu_mb_stat':
> arch/powerpc/platforms/cell/spufs/switch.c:1660:6: warning:
> variable ‘dummy’ set but not used [-Wunused-but-set-
On Tue, 1 Jun 2021 16:53:19 +0800, Baokun Li wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> arch/powerpc/platforms/cell/spider-pci.c: In function 'spiderpci_io_flush':
> arch/powerpc/platforms/cell/spider-pci.c:28:6: warning:
> variable ‘val’ set but not used [-Wunused-but-set-variabl
On Fri, 04 Jun 2021 15:58:25 +, Geoff Levand wrote:
> Change the PS3 linker script to align the DTB at 8 bytes,
> the same alignment as that of the of the 'generic' powerpc
> linker script.
Applied to powerpc/next.
[2/2] powerpc/ps3: Re-align DTB in image
https://git.kernel.org/powerpc/
On Thu, 03 Jun 2021 19:16:56 +, Geoff Levand wrote:
> This is a set of patches that fix various DMA related problems in the PS3
> device drivers, and add better error checking and improved message logging.
>
> Changes from V1:
> Split the V1 series into two, one series with powerpc changes,
On Fri, 04 Jun 2021 15:58:25 +, Geoff Levand wrote:
> I've rebased the V1 patches to v5.13-rc4, and moved the firmware version
> export
> from procfs to sysfs/firmware.
>
> Please consider.
>
> -Geoff
>
> [...]
Applied to powerpc/next.
[1/2] powerpc/ps3: Add firmware version to sysfs
On Fri, 11 Jun 2021 17:58:27 +1000, Finn Thain wrote:
> This avoids an (optional) compiler warning:
>
> arch/powerpc/kernel/tau_6xx.c: In function 'TAU_init':
> arch/powerpc/kernel/tau_6xx.c:204:30: error: too many arguments for format
> [-Werror=format-extra-args]
> tau_workq = alloc_workqueue
On Mon, 14 Jun 2021 22:09:07 +1000, Daniel Axtens wrote:
> Make our stack-walking code KASAN-safe by using __no_sanitize_address.
> Generic code, arm64, s390 and x86 all make accesses unchecked for similar
> sorts of reasons: when unwinding a stack, we might touch memory that KASAN
> has marked as
On Thu, 3 Jun 2021 09:29:02 + (UTC), Christophe Leroy wrote:
> Instead of duplicating the update of BDI2000 pointers in
> set_context(), do it directly from switch_mmu_context().
Applied to powerpc/next.
[1/6] powerpc/nohash: Refactor update of BDI2000 pointers in
switch_mmu_context()
On Fri, 4 Jun 2021 04:49:25 + (UTC), Christophe Leroy wrote:
> PPC64 uses MMU features to enable/disable KUAP at boot time.
> But feature fixups are applied way too early on PPC32.
>
> But since commit c16728835eec ("powerpc/32: Manage KUAP in C"),
> all KUAP is in C so it is now possible to u
On Thu, 3 Jun 2021 08:41:35 + (UTC), Christophe Leroy wrote:
> This series is a rework of KUAP on book3s/32.
>
> On book3s32, KUAP is heavier than on other platform because it can't
> be opened globaly at once, it must be done for each 256Mb segment.
>
> Instead of opening access to all neces
On Thu, 20 May 2021 13:50:37 + (UTC), Christophe Leroy wrote:
> This series is a cleanup of the use of 'struct ppc_inst'.
>
> A confusion is made between internal representation of powerpc
> instructions with 'struct ppc_inst' and in-memory code which is
> and will always be an array of 'unsig
On Thu, 20 May 2021 10:23:00 + (UTC), Christophe Leroy wrote:
> At the time being, we have PPC_RAW_PLXVP() and PPC_RAW_PSTXVP() which
> provide a 64 bits value, and then it gets split by open coding to
> format it into a 'struct ppc_inst' instruction.
>
> Instead, define a PPC_RAW_xxx_P() and
On Thu, 10 Jun 2021 15:58:34 + (UTC), Christophe Leroy wrote:
> PPC_TRANSACTIONAL_MEM is only on book3s/64
> SPE is only on booke
>
> PPC_TRANSACTIONAL_MEM selects ALTIVEC and VSX
>
> Therefore, within PPC_TRANSACTIONAL_MEM sections,
> ALTIVEC and VSX are always defined while SPE never is.
>
On Fri, 4 Jun 2021 12:31:09 + (UTC), Christophe Leroy wrote:
> gettid() is 10% lighter than getppid(), use it for null_syscall selftest.
Applied to powerpc/next.
[1/1] powerpc/selftests: Use gettid() instead of getppid() for null_syscall
https://git.kernel.org/powerpc/c/a1ea0ca8a6f17d7b
On Wed, 9 Jun 2021 05:52:50 + (UTC), Christophe Leroy wrote:
> proc_trap() has never been used, remove it.
Applied to powerpc/next.
[1/1] powerpc: Remove proc_trap()
https://git.kernel.org/powerpc/c/77b0bed74232c480b94bae188b6c7cd0ddee92e8
cheers
On Thu, 3 Jun 2021 07:53:49 + (UTC), Christophe Leroy wrote:
> Since commit Fixes: 555904d07eef ("powerpc/8xx: MM_SLICE is not needed
> anymore"),
> CONFIG_PPC_MMU_NOHASH_32 has not been used.
>
> Remove it.
Applied to powerpc/next.
[1/1] powerpc: Remove CONFIG_PPC_MMU_NOHASH_32
https
On Fri, 14 May 2021 13:14:53 + (UTC), Christophe Leroy wrote:
> _switch() saves and restores ALTIVEC and SPE status.
> For altivec this is redundant with what __switch_to() does with
> save_sprs() and restore_sprs() and giveup_all() before
> calling _switch().
>
> Add support for SPI in save_s
On Fri, 11 Jun 2021 19:08:54 + (UTC), Christophe Leroy wrote:
> book3s/32 and 8xx don't use vmalloc for modules.
>
> Print the modules area at startup as part of the virtual memory layout:
>
> [0.00] Kernel virtual memory layout:
> [0.00] * 0xffafc000..0xc000 : fixmap
>
On Tue, 8 Jun 2021 17:22:51 + (UTC), Christophe Leroy wrote:
> Comment says that __main() is there to make GCC happy.
>
> It's been there since the implementation of ppc arch in Linux 1.3.45.
>
> ppc32 is the only architecture having that. Even ppc64 doesn't have it.
>
> Seems like GCC is st
On Wed, 2 Jun 2021 06:42:10 + (UTC), Christophe Leroy wrote:
> Powerpc 44x has two bits for exec protection in TLBs: one
> for user (UX) and one for superviser (SX).
>
> Clear SX on user pages in TLB miss handlers to provide KUEP.
Applied to powerpc/next.
[1/1] powerpc/44x: Implement Kernel
On Fri, 7 May 2021 14:01:09 + (UTC), Christophe Leroy wrote:
> arch/powerpc/Kbuild decend into arch/powerpc/perf/ only when
> CONFIG_PERF_EVENTS is selected, so there is not need to take
> CONFIG_PERF_EVENTS into account in arch/powerpc/perf/Makefile.
Applied to powerpc/next.
[1/1] powerpc/pe
On Thu, 10 Jun 2021 14:06:39 +0530, Aneesh Kumar K.V wrote:
> Update _tlbiel_pid() such that we can avoid build errors like below when
> using this function in other places.
>
> arch/powerpc/mm/book3s64/radix_tlb.c: In function
> ‘__radix__flush_tlb_range_psize’:
> arch/powerpc/mm/book3s64/radix_
On Wed, 9 Jun 2021 06:10:29 + (UTC), Christophe Leroy wrote:
> update_power8_hid0() is used only by powernv platform subcore.c
>
> Move it there.
Applied to powerpc/next.
[1/1] powerpc: Move update_power8_hid0() into its only user
https://git.kernel.org/powerpc/c/ab3aab292cb2f417f63b8f
On Thu, 3 Jun 2021 09:13:54 + (UTC), Christophe Leroy wrote:
> All KUAP helpers defined in asm/kup.h are single line functions
> that should be inlined. But on book3s/32 build, we get many
> instances of .
>
> Force inlining of those helpers.
Applied to powerpc/next.
[1/1] powerpc/kuap: Forc
On Tue, 11 May 2021 06:08:06 + (UTC), Christophe Leroy wrote:
> Commit 328e7e487a46 ("powerpc: force inlining of csum_partial() to
> avoid multiple csum_partial() with GCC10") inlined csum_partial().
>
> Now that csum_partial() is inlined, GCC outlines csum_add() when
> called by csum_partial(
On Mon, 7 Jun 2021 10:56:04 + (UTC), Christophe Leroy wrote:
> At the time being, empty_zero_page[] is defined in each
> platform head.S.
>
> Define it in mm/mem.c instead, and put it in BSS section instead
> of the DATA section. Commit 5227cfa71f9e ("arm64: mm: place
> empty_zero_page in bss"
On Fri, 11 Jun 2021 19:10:57 + (UTC), Christophe Leroy wrote:
> linux/processor.h has exactly same defination for spin_until_cond.
> Drop the redundant defination in asm/processor.h
Applied to powerpc/next.
[1/2] powerpc/64: drop redundant defination of spin_until_cond
https://git.kerne
On Tue, 25 May 2021 09:51:41 -0400, Athira Rajeev wrote:
> The "no_handler_test" in ebb selftests attempts to read the PMU
> registers after closing of the event via helper function
> "dump_ebb_state". With the MMCR0 control bit (PMCCEXT) in ISA v3.1,
> read access to group B registers is restricte
On Mon, 10 May 2021 17:49:25 +0300, Andy Shevchenko wrote:
> If by some reason any of the headers will include ctype.h
> we will have a name collision. Avoid this by moving isspace()
> to the dedicate namespace.
>
> First appearance of the code is in the commit cf68787b68a2
> ("powerpc/prom_init:
Microwatt's hardware RNG is accessed using the DARN instruction.
Signed-off-by: Paul Mackerras
---
arch/powerpc/platforms/microwatt/Kconfig | 1 +
arch/powerpc/platforms/microwatt/Makefile | 2 +-
arch/powerpc/platforms/microwatt/rng.c| 48 +++
3 files changed, 50 inse
This series of patches adds support for the Microwatt soft-core.
Microwatt is an open-source 64-bit Power ISA processor written in VHDL
which targets medium-sized FPGAs such as the Xilinx Artix-7 or the
Lattice ECP5. Microwatt currently implements the scalar fixed plus
floating-point subset of Pow
From: Benjamin Herrenschmidt
This is a simple native ICS backend that matches the layout of
the Microwatt implementation of ICS.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 18 ++
arch/powerpc/platforms/microwatt/Kconfig
From: Benjamin Herrenschmidt
Just like any other embedded platform.
Add an empty soc node.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 7 +++
arch/powerpc/platforms/microwatt/setup.c | 8
2 files changed, 15
Microwatt is a FPGA-based implementation of the Power ISA. It
currently only implements little-endian 64-bit mode, and does
not (yet) support SMP, VMX, VSX or transactional memory. It has an
optional FPU, and an optional MMU (required for running Linux,
obviously) which implements a configurable
From: Benjamin Herrenschmidt
This fixes the core devtree.c functions and the ns16550 UART backend.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/devtree.c | 59 +
arch/powerpc/boot/ns16550.c | 9 --
2 files c
From: Joel Stanley
This allows microwatt's kernel to be built with an embedded device tree.
Load to arch/powerpc/boot/dtbImage.microwatt to 0x50:
mw_debug -b fpga stop load arch/powerpc/boot/dtbImage.microwatt 50 start
Signed-off-by: Joel Stanley
Signed-off-by: Paul Mackerras
---
a
Microwatt currently runs with MSR[HV] = 0, hence the usable-privilege
properties don't have bit 2 (for HV support) set, and we need the
/chosen/ibm,architecture-vec-5 property.
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 98 +
1 file change
From: Benjamin Herrenschmidt
This adds support to the Microwatt platform to use the standard
16550-style UART which available in the standalone Microwatt FPGA.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 27 ---
Signed-off-by: Paul Mackerras
---
arch/powerpc/configs/microwatt_defconfig | 98
1 file changed, 98 insertions(+)
create mode 100644 arch/powerpc/configs/microwatt_defconfig
diff --git a/arch/powerpc/configs/microwatt_defconfig
b/arch/powerpc/configs/microwatt_defconfi
On Tue, 8 Jun 2021 23:46:05 +1000, Michael Ellerman wrote:
> In commit 96d7a4e06fab ("powerpc/signal64: Rewrite handle_rt_signal64()
> to minimise uaccess switches") the 64-bit signal code was rearranged to
> use user_write_access_begin/end().
>
> As part of that change the call to copy_siginfo_to
On Mon, 14 Jun 2021 23:14:40 +1000, Michael Ellerman wrote:
> Commit b0b3b2c78ec0 ("powerpc: Switch to relative jump labels") switched
> us to using relative jump labels. That involves changing the code,
> target and key members in struct jump_entry to be relative to the
> address of the jump_entry
On Sat, 5 Jun 2021 08:56:09 + (UTC), Christophe Leroy wrote:
> Commit b26e8f27253a ("powerpc/mem: Move cache flushing functions into
> mm/cacheflush.c") removed asm/sparsemem.h which is required when
> CONFIG_MEMORY_HOTPLUG is selected to get the declaration of
> create_section_mapping().
>
>
On Wed, Jun 16, 2021 at 4:51 AM Ondrej Mosnacek wrote:
>
> Commit 59438b46471a ("security,lockdown,selinux: implement SELinux
> lockdown") added an implementation of the locked_down LSM hook to
> SELinux, with the aim to restrict which domains are allowed to perform
> operations that would breach
On Thu, Jun 17, 2021 at 08:01:57PM -0700, Ira Weiny wrote:
>
> > + flush_kernel_dcache_page(__page); \
>
> Is this required on 32bit systems? Why is kunmap_flush_on_unmap() not
> sufficient on 64bit systems? The normal kunmap_local() path does that.
>
> I'm sorry but I d
On 6/18/21 1:30 AM, Daniel Henrique Barboza wrote:
On 6/17/21 8:11 AM, Aneesh Kumar K.V wrote:
Daniel Henrique Barboza writes:
On 6/17/21 4:46 AM, David Gibson wrote:
On Tue, Jun 15, 2021 at 12:35:17PM +0530, Aneesh Kumar K.V wrote:
David Gibson writes:
In fact, the more I speak a
On Tue, Jun 15, 2021 at 03:24:39PM +0200, Christoph Hellwig wrote:
> Add a helper that calls flush_kernel_dcache_page before unmapping the
> local mapping. flush_kernel_dcache_page is required for all pages
> potentially mapped into userspace that were written to using kmap*,
> so having a helper
On Thu, Jun 17, 2021 at 02:41:28PM +1000, Michael Ellerman wrote:
> Paul Mackerras writes:
> >
>
> Little bit of change log never hurts :)
>
> > Signed-off-by: Paul Mackerras
> > ---
> > arch/powerpc/boot/dts/microwatt.dts | 105
> > 1 file changed, 105 insertions(
On Fri, 2021-06-18 at 09:34 +1000, Nicholas Piggin wrote:
> Excerpts from Haren Myneni's message of June 18, 2021 6:37 am:
> > NX generates an interrupt when sees a fault on the user space
> > buffer and the hypervisor forwards that interrupt to OS. Then
> > the kernel handles the interrupt by issu
On 6/17/21 8:16 AM, Mathieu Desnoyers wrote:
> - On Jun 15, 2021, at 11:21 PM, Andy Lutomirski l...@kernel.org wrote:
>
> [...]
>
>> +# An architecture that wants to support
>> +# MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE needs to define precisely what
>> it
>> +# is supposed to do and impl
On 6/17/21 7:47 AM, Mathieu Desnoyers wrote:
> Please change back this #ifndef / #else / #endif within function for
>
> if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE)) {
> ...
> } else {
> ...
> }
>
> I don't think mixing up preprocessor and code logic makes it more readable.
I agree
https://bugzilla.kernel.org/show_bug.cgi?id=213079
Erhard F. (erhar...@mailbox.org) changed:
What|Removed |Added
Attachment #296759|0 |1
is obsolete|
https://bugzilla.kernel.org/show_bug.cgi?id=213079
--- Comment #9 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 297437
--> https://bugzilla.kernel.org/attachment.cgi?id=297437&action=edit
dmesg (5.13-rc6 w. patch fbbefb3 reverted + debug, PowerMac G5 11,2)
--
You may reply to th
https://bugzilla.kernel.org/show_bug.cgi?id=213079
--- Comment #8 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 297435
--> https://bugzilla.kernel.org/attachment.cgi?id=297435&action=edit
dmesg (5.13-rc6 + debug, PowerMac G5 11,2)
--
You may reply to this email to add a comment.
https://bugzilla.kernel.org/show_bug.cgi?id=213079
--- Comment #7 from Erhard F. (erhar...@mailbox.org) ---
(In reply to Oliver O'Halloran from comment #5)
> Could you add "debug" to the kernel command line and post the dmesg output
> for a boot with the patch applied and reverted?
Ok, on top of 5
Excerpts from Haren Myneni's message of June 18, 2021 6:39 am:
>
> Export NX-GZIP capabilities to usrespace in sysfs
> /sys/devices/vio/ibm,compression-v1/nx_gzip_caps directory.
> These are queried by userspace accelerator libraries to set
> minimum length heuristics and maximum limits on request
Excerpts from Haren Myneni's message of June 18, 2021 6:38 am:
>
> The hypervisor provides different NX capabilities that it
> supports. These capabilities such as recommended minimum
> compression / decompression lengths and the maximum request
> buffer size in bytes are used to define the user s
Excerpts from Haren Myneni's message of June 18, 2021 6:37 am:
>
> NX generates an interrupt when sees a fault on the user space
> buffer and the hypervisor forwards that interrupt to OS. Then
> the kernel handles the interrupt by issuing H_GET_NX_FAULT hcall
> to retrieve the fault CRB informatio
On Thu, 17 Jun 2021, Claire Chang wrote:
> Add the functions, swiotlb_{alloc,free} and is_swiotlb_for_alloc to
> support the memory allocation from restricted DMA pool.
>
> The restricted DMA pool is preferred if available.
>
> Note that since coherent allocation needs remapping, one must set up
On Thu, 17 Jun 2021, Claire Chang wrote:
> Propagate the swiotlb_force into io_tlb_default_mem->force_bounce and
> use it to determine whether to bounce the data or not. This will be
> useful later to allow for different pools.
>
> Signed-off-by: Claire Chang
> Reviewed-by: Christoph Hellwig
> T
On Thu, 17 Jun 2021, Claire Chang wrote:
> Update is_swiotlb_active to add a struct device argument. This will be
> useful later to allow for different pools.
>
> Signed-off-by: Claire Chang
> Reviewed-by: Christoph Hellwig
> Tested-by: Stefano Stabellini
> Tested-by: Will Deacon
Acked-by: St
On Thu, 17 Jun 2021, Claire Chang wrote:
> Update is_swiotlb_buffer to add a struct device argument. This will be
> useful later to allow for different pools.
>
> Signed-off-by: Claire Chang
> Reviewed-by: Christoph Hellwig
> Tested-by: Stefano Stabellini
> Tested-by: Will Deacon
Acked-by: St
On Thu, 17 Jun 2021, Claire Chang wrote:
> Always have the pointer to the swiotlb pool used in struct device. This
> could help simplify the code for other pools.
>
> Signed-off-by: Claire Chang
> Reviewed-by: Christoph Hellwig
> Tested-by: Stefano Stabellini
> Tested-by: Will Deacon
Acked-by
On Thu, 17 Jun 2021, Claire Chang wrote:
> Add a new function, swiotlb_init_io_tlb_mem, for the io_tlb_mem struct
> initialization to make the code reusable.
>
> Signed-off-by: Claire Chang
> Reviewed-by: Christoph Hellwig
> Tested-by: Stefano Stabellini
> Tested-by: Will Deacon
> ---
> kerne
Excerpts from Haren Myneni's message of June 18, 2021 6:31 am:
>
> PowerNV uses registers to open/close VAS windows, and getting the
> paste address. Whereas the hypervisor calls are used on PowerVM.
>
> This patch adds the platform specific user space window operations
> and register with the co
Excerpts from Haren Myneni's message of June 18, 2021 6:35 am:
>
> The hypervisor provides VAS capabilities for GZIP default and QoS
> features. These capabilities gives information for the specific
> features such as total number of credits available in LPAR,
> maximum credits allowed per window,
Excerpts from Haren Myneni's message of June 18, 2021 6:36 am:
>
> This patch adds VAS window allocatioa/close with the corresponding
> hcalls. Also changes to integrate with the existing user space VAS
> API and provide register/unregister functions to NX pseries driver.
>
> The driver register
Excerpts from Haren Myneni's message of June 18, 2021 6:32 am:
>
> If a coprocessor encounters an error translating an address, the
> VAS will cause an interrupt in the host. The kernel processes
> the fault by updating CSB. This functionality is same for both
> powerNV and pseries. So this patch
allnoconfig
i386 randconfig-a002-20210617
i386 randconfig-a006-20210617
i386 randconfig-a001-20210617
i386 randconfig-a004-20210617
i386 randconfig-a005-20210617
i386 randconfig
The user space uses /dev/crypto/nx-gzip interface to setup VAS
windows, create paste mapping and close windows. This patch adds
changes to create/remove this interface with VAS register/unregister
functions on PowerVM platform.
Signed-off-by: Haren Myneni
Acked-by: Herbert Xu
Acked-by: Nichola
Export NX-GZIP capabilities to usrespace in sysfs
/sys/devices/vio/ibm,compression-v1/nx_gzip_caps directory.
These are queried by userspace accelerator libraries to set
minimum length heuristics and maximum limits on request sizes.
NX-GZIP capabilities:
min_compress_len /*Recommended minimum c
The hypervisor provides different NX capabilities that it
supports. These capabilities such as recommended minimum
compression / decompression lengths and the maximum request
buffer size in bytes are used to define the user space NX
request.
NX will reject the request if the buffer size is more
Rename nx-842-pseries.c to nx-common-pseries.c to add code for new
GZIP compression type. The actual functionality is not changed in
this patch.
Signed-off-by: Haren Myneni
Acked-by: Herbert Xu
Acked-by: Nicholas Piggin
---
drivers/crypto/nx/Makefile | 2 +-
NX generates an interrupt when sees a fault on the user space
buffer and the hypervisor forwards that interrupt to OS. Then
the kernel handles the interrupt by issuing H_GET_NX_FAULT hcall
to retrieve the fault CRB information.
This patch also adds changes to setup and free IRQ per each
window a
This patch adds VAS window allocatioa/close with the corresponding
hcalls. Also changes to integrate with the existing user space VAS
API and provide register/unregister functions to NX pseries driver.
The driver register function is used to create the user space
interface (/dev/crypto/nx-gzip)
The hypervisor provides VAS capabilities for GZIP default and QoS
features. These capabilities gives information for the specific
features such as total number of credits available in LPAR,
maximum credits allowed per window, maximum credits allowed in
LPAR, whether usermode copy/paste is support
This patch adds the following hcall wrapper functions to allocate,
modify and deallocate VAS windows, and retrieve VAS capabilities.
H_ALLOCATE_VAS_WINDOW: Allocate VAS window
H_DEALLOCATE_VAS_WINDOW: Close VAS window
H_MODIFY_VAS_WINDOW: Setup window before using
H_QUERY_VAS_CAPABILITIES: Get V
PowerVM introduces two different type of credits: Default and Quality
of service (QoS).
The total number of default credits available on each LPAR depends
on CPU resources configured. But these credits can be shared or
over-committed across LPARs in shared mode which can result in
paste command
This patch adds hcalls and other definitions. Also define structs
that are used in VAS implementation on PowerVM.
Signed-off-by: Haren Myneni
Acked-by: Nicholas Piggin
---
arch/powerpc/include/asm/hvcall.h| 7 ++
arch/powerpc/include/asm/vas.h | 30 +++
arch/powerpc/platforms
Many elements in vas_struct are used on PowerNV and PowerVM
platforms. vas_window is used for both TX and RX windows on
PowerNV and for TX windows on PowerVM. So some elements are
specific to these platforms.
So this patch defines common vas_window and platform
specific window structs (pnv_vas_w
If a coprocessor encounters an error translating an address, the
VAS will cause an interrupt in the host. The kernel processes
the fault by updating CSB. This functionality is same for both
powerNV and pseries. So this patch moves these functions to
common vas-api.c and the actual functionality i
Take pid and mm references when each window opens and drops during
close. This functionality is needed for powerNV and pseries. So
this patch defines the existing code as functions in common book3s
platform vas-api.c
Signed-off-by: Haren Myneni
Reviewed-by: Nicholas Piggin
---
arch/powerpc/in
PowerNV uses registers to open/close VAS windows, and getting the
paste address. Whereas the hypervisor calls are used on PowerVM.
This patch adds the platform specific user space window operations
and register with the common VAS user space interface.
Signed-off-by: Haren Myneni
Reviewed-by:
powerNV and pseries drivers register / unregister to the corresponding
platform specific VAS separately. Then these VAS functions call the
common API with the specific window operations. So rename powerNV VAS
API register/unregister functions.
Signed-off-by: Haren Myneni
Reviewed-by: Nicholas P
The pseries platform will share vas and nx code and interfaces
with the PowerNV platform, so create the
arch/powerpc/platforms/book3s/ directory and move VAS API code
there. Functionality is not changed.
Signed-off-by: Haren Myneni
Reviewed-by: Nicholas Piggin
---
arch/powerpc/include/asm/vas
The kernel handles the NX fault by updating CSB or sending
signal to process. In multithread applications, children can
open VAS windows and can exit without closing them. But the
parent can continue to send NX requests with these windows. To
prevent pid reuse, reference will be taken on pid and
Virtual Accelerator Switchboard (VAS) allows kernel subsystems
and user space processes to directly access the Nest Accelerator
(NX) engines which provides HW compression. The true user mode
VAS/NX support on PowerNV is already included in Linux. Whereas
PowerVM support is available from P10 onwa
onfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20210617
x86_64
On 6/17/21 8:11 AM, Aneesh Kumar K.V wrote:
Daniel Henrique Barboza writes:
On 6/17/21 4:46 AM, David Gibson wrote:
On Tue, Jun 15, 2021 at 12:35:17PM +0530, Aneesh Kumar K.V wrote:
David Gibson writes:
On Tue, Jun 15, 2021 at 11:27:50AM +0530, Aneesh Kumar K.V wrote:
David Gibson wr
allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a002-20210617
i386 randconfig-a006-20210617
i386
On systems without any specific PMU driver support registered, running
perf record causes Oops.
The relevant portion from call trace:
BUG: Kernel NULL pointer dereference on read at 0x0040
Faulting instruction address: 0xc0021f0c
Oops: Kernel access of bad area, sig: 11 [#1]
BE PAGE_SIZE=4K P
> On 17-Jun-2021, at 10:05 PM, Christophe Leroy
> wrote:
>
>
>
> Le 17/06/2021 à 08:36, Athira Rajeev a écrit :
>>> On 16-Jun-2021, at 11:56 AM, Christophe Leroy
>>> wrote:
>>>
>>>
>>>
>>> Le 16/06/2021 à 05:40, Athira Rajeev a écrit :
> On 16-Jun-2021, at 8:53 AM, Madhavan Sriniva
On Thu, Jun 17, 2021 at 11:40:23AM +1000, Nicholas Piggin wrote:
> Excerpts from Segher Boessenkool's message of June 17, 2021 9:37 am:
> > On Tue, Jun 15, 2021 at 09:05:27AM +1000, Paul Mackerras wrote:
> >> This ensures that we don't get a decrementer interrupt arriving before
> >> we have set up
PAPR interface currently supports two different ways of communicating resource
grouping details to the OS. These are referred to as Form 0 and Form 1
associativity grouping. Form 0 is the older format and is now considered
deprecated. This patch adds another resource grouping named FORM2.
Signed-o
This helper is only used with the dispatch trace log collection.
A later patch will add Form2 affinity support and this change helps
in keeping that simpler. Also add a comment explaining we don't expect
the code to be called with FORM0
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
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