Fixed the eventcode values in the power10 json event files to append
"0x" since these are hexadecimal values.
Patch also changes event description of PM_EXEC_STALL_LOAD_FINISH and
PM_EXEC_STALL_NTC_FLUSH event and move some events to correct files.
Fixes: 32daa5d7899e ("perf vendor events: Initial
On Mon, May 24, 2021 at 11:49 PM Konrad Rzeszutek Wilk
wrote:
>
> On Tue, May 18, 2021 at 02:48:35PM +0800, Claire Chang wrote:
> > I didn't move this to a separate file because I feel it might be
> > confusing for swiotlb_alloc/free (and need more functions to be
> > non-static).
> > Maybe instea
On Mon, May 24, 2021 at 11:51 PM Konrad Rzeszutek Wilk
wrote:
>
> On Tue, May 18, 2021 at 02:51:52PM +0800, Claire Chang wrote:
> > Still keep this function because directly using dev->dma_io_tlb_mem
> > will cause issues for memory allocation for existing devices. The pool
> > can't support atomi
On Mon, May 24, 2021 at 11:53 PM Konrad Rzeszutek Wilk
wrote:
>
> > > do the set_memory_decrypted()+memset(). Is this okay or should
> > > swiotlb_init_io_tlb_mem() add an additional argument to do this
> > > conditionally?
> >
> > I'm actually not sure if this it okay. If not, will add an additio
On Thu, May 20, 2021 at 3:58 AM Christian Brauner
wrote:
> On Wed, May 19, 2021 at 04:00:21PM -0400, Richard Guy Briggs wrote:
> > The openat2(2) syscall was added in kernel v5.6 with commit fddb5d430ad9
> > ("open: introduce openat2(2) syscall")
> >
> > Add the openat2(2) syscall to the audit sys
Matheus Castanho writes:
> Dmitry V. Levin writes:
>
>> On Fri, May 21, 2021 at 05:00:36PM -0300, Matheus Castanho wrote:
>>> Florian Weimer writes:
>>> > * Matheus Castanho via Libc-alpha:
>>> >> From: Nicholas Piggin
>>> >> Subject: [PATCH 1/1] powerpc: Fix handling of scv return error cod
On Mon, May 24, 2021 at 3:38 AM Aneesh Kumar K.V
wrote:
>
> Avoid the above race with MOVE_PMD by holding pte ptl in mremap and waiting
> for
> parallel pagetable walk to finish operating on pte before updating new_pmd
Ack on the concept.
However, not so much on the patch.
Odd whitespace chang
On Sun, May 23, 2021 at 11:04 PM Aneesh Kumar K.V
wrote:
>
> Add new helper flush_pte_tlb_pwc_range() which invalidates both TLB and
> page walk cache where TLB entries are mapped with page size PAGE_SIZE.
So I dislike this patch for two reasons:
(a) naming.
If the ppc people want to use crazy
> > do the set_memory_decrypted()+memset(). Is this okay or should
> > swiotlb_init_io_tlb_mem() add an additional argument to do this
> > conditionally?
>
> I'm actually not sure if this it okay. If not, will add an additional
> argument for it.
Any observations discovered? (Want to make sure my
On Tue, May 18, 2021 at 02:51:52PM +0800, Claire Chang wrote:
> Still keep this function because directly using dev->dma_io_tlb_mem
> will cause issues for memory allocation for existing devices. The pool
> can't support atomic coherent allocation so we need to distinguish the
> per device pool and
On Tue, May 18, 2021 at 02:48:35PM +0800, Claire Chang wrote:
> I didn't move this to a separate file because I feel it might be
> confusing for swiotlb_alloc/free (and need more functions to be
> non-static).
> Maybe instead of moving to a separate file, we can try to come up with
> a better namin
* Valentin Schneider [2021-05-24 15:16:09]:
> On 21/05/21 14:58, Srikar Dronamraju wrote:
> > * Peter Zijlstra [2021-05-21 10:14:10]:
> >
> >> On Fri, May 21, 2021 at 08:08:02AM +0530, Srikar Dronamraju wrote:
> >> > * Peter Zijlstra [2021-05-20 20:56:31]:
> >> >
> >> > > On Thu, May 20, 2021 a
* Valentin Schneider [2021-05-24 15:16:22]:
> On 20/05/21 21:14, Srikar Dronamraju wrote:
> > +int arch_populate_distance_map(unsigned long *distance_map)
> > +{
> > + int i;
> > + int distance = LOCAL_DISTANCE;
> > +
> > + bitmap_set(distance_map, distance, 1);
> > +
> > + if (!form1_aff
Linus Torvalds writes:
> On Fri, May 21, 2021 at 3:04 AM Aneesh Kumar K.V
> wrote:
>>
>> We could do MOVE_PMD with something like below? A equivalent MOVE_PUD
>> will be costlier which makes me wonder whether we should even support that?
>
> Well, without USE_SPLIT_PTE_PTLOCKS the pud case would
On 20/05/21 21:14, Srikar Dronamraju wrote:
> +int arch_populate_distance_map(unsigned long *distance_map)
> +{
> + int i;
> + int distance = LOCAL_DISTANCE;
> +
> + bitmap_set(distance_map, distance, 1);
> +
> + if (!form1_affinity) {
> + bitmap_set(distance_map, REMOTE
On 21/05/21 14:58, Srikar Dronamraju wrote:
> * Peter Zijlstra [2021-05-21 10:14:10]:
>
>> On Fri, May 21, 2021 at 08:08:02AM +0530, Srikar Dronamraju wrote:
>> > * Peter Zijlstra [2021-05-20 20:56:31]:
>> >
>> > > On Thu, May 20, 2021 at 09:14:25PM +0530, Srikar Dronamraju wrote:
>> > > > Curren
CPU 1 CPU 2 CPU 3
mremap(old_addr, new_addr) page_shrinker/try_to_unmap_one
addr = old_addr
lock(pte_ptl)
lock(pmd_ptl)
pmd = *old_pmd
pmd_clear(old_pmd)
flush_tlb_rang
CPU 1 CPU 2 CPU 3
mremap(old_addr, new_addr) page_shrinker/try_to_unmap_one
addr = old_addr
lock(pte_ptl)
lock(pmd_ptl)
pmd = *old_pmd
pmd_clear(old_pmd)
flush_tlb_rang
Nicholas Piggin writes:
> Similar to commit 25edcc50d76c ("KVM: PPC: Book3S HV: Save and restore
> FSCR in the P9 path"), ensure the P7/8 path saves and restores the host
> FSCR. The logic explained in that patch actually applies there to the
> old path well: a context switch can be made before k
Dmitry V. Levin writes:
> On Fri, May 21, 2021 at 05:00:36PM -0300, Matheus Castanho wrote:
>> Florian Weimer writes:
>> > * Matheus Castanho via Libc-alpha:
>> >> From: Nicholas Piggin
>> >> Subject: [PATCH 1/1] powerpc: Fix handling of scv return error codes
>> >>
>> >> When using scv on te
Both these config options are generally enabled in distro kernels.
Enable the same in a few powerpc64 configs to get better coverage and
testing.
Signed-off-by: Naveen N. Rao
---
arch/powerpc/configs/powernv_defconfig | 1 +
arch/powerpc/configs/ppc64_defconfig | 2 ++
arch/powerpc/configs/pse
The simple_strtol() function is deprecated in some situation since
it does not check for the range overflow. Use kstrtoint() instead.
Signed-off-by: Liu Shixin
---
drivers/macintosh/therm_adt746x.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/macintosh/therm_
Some architectures do have the concept of page walk cache which need
to be flush when updating higher levels of page tables. A fast mremap
that involves moving page table pages instead of copying pte entries
should flush page walk cache since the old translation cache is no more
valid.
Add new hel
mremap HAVE_MOVE_PMD/PUD optimization time comparison for 1GB region:
1GB mremap - Source PTE-aligned, Destination PTE-aligned
mremap time: 1122062ns
1GB mremap - Source PMD-aligned, Destination PMD-aligned
mremap time: 522062ns
1GB mremap - Source PUD-aligned, Destination PUD-aligne
CPU 1 CPU 2 CPU 3
mremap(old_addr, new_addr) page_shrinker/try_to_unmap_one
addr = old_addr
lock(pte_ptl)
lock(pmd_ptl)
pmd = *old_pmd
pmd_clear(old_pmd)
flush_tlb_rang
Architectures like ppc64 support faster mremap only with radix
translation. Hence allow a runtime check w.r.t support for fast mremap.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/tlb.h | 6 ++
mm/mremap.c| 15 ++-
2 files changed, 20 insertio
As explained in
commit eb66ae030829 ("mremap: properly flush TLB before releasing the page")
mremap is special in that it doesn't take ownership of the page. The
optimized version for PUD/PMD aligned mremap also doesn't hold the ptl lock.
Hence flush the TLB before we update the new page table loca
No functional change in this patch
Signed-off-by: Aneesh Kumar K.V
---
.../include/asm/book3s/64/tlbflush-radix.h| 19 +++-
arch/powerpc/include/asm/book3s/64/tlbflush.h | 23 ---
arch/powerpc/mm/book3s64/radix_hugetlbpage.c | 4 +--
arch/powerpc/mm/book3s64/radix_tlb.c
pmd/pud_populate is the right interface to be used to set the respective
page table entries. Some architectures like ppc64 do assume that set_pmd/pud_at
can only be used to set a hugepage PTE. Since we are not setting up a hugepage
PTE here, use the pmd/pud_populate interface.
Signed-off-by: Anees
Update _tlbiel_pid() such that we can avoid build errors like below when
using this function in other places.
arch/powerpc/mm/book3s64/radix_tlb.c: In function
‘__radix__flush_tlb_range_psize’:
arch/powerpc/mm/book3s64/radix_tlb.c:114:2: warning: ‘asm’ operand 3 probably
does not match constrain
With a large mmap map size, we can overlap with the text area and using
MAP_FIXED results in unmapping that area. Switch to MAP_FIXED_NOREPLACE
and handle the EEXIST error.
Reviewed-by: Kalesh Singh
Signed-off-by: Aneesh Kumar K.V
---
tools/testing/selftests/vm/mremap_test.c | 5 +++--
1 file c
Instead of hardcoding 4K page size fetch it using sysconf(). For the performance
measurements test still assume 2M and 1G are hugepage sizes.
Reviewed-by: Kalesh Singh
Signed-off-by: Aneesh Kumar K.V
---
tools/testing/selftests/vm/mremap_test.c | 113 ---
1 file changed, 61
With TRANSPARENT_HUGEPAGE_PUD enabled the kernel can find huge PUD entries.
Add a helper to move huge PUD entries on mremap().
This will be used by a later patch to optimize mremap of PUD_SIZE aligned
level 4 PTE mapped address
This also make sure we support mremap on huge PUD entries even with
C
This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires
the platform to support updating higher-level page tables without
updating page table entries. This also needs to invalidate the Page Walk
Cache on architecture supporting the same.
Changes from v5:
* Drop patch mm/mremap: M
On 5/24/21 9:26 AM, Christoph Hellwig wrote:
On Sun, May 23, 2021 at 10:12:49AM +0200, Hannes Reinecke wrote:
+ blk_set_stacking_limits(&mddev->queue->limits);
blk_queue_write_cache(mddev->queue, true, true);
/* Allow extended partitions. This makes the
* 'mdp' de
Christophe Leroy writes:
> Nicholas Piggin a écrit :
>
>> real_vmalloc_addr() does not currently work for huge vmalloc, which is
>> what the reverse map can be allocated with for radix host, hash guest.
>>
>> Add huge page awareness to the function.
>>
>> Fixes: 8abddd968a30 ("powerpc/64s/radix:
On Sun, May 23, 2021 at 10:20:27AM +0200, Hannes Reinecke wrote:
> What about the check for GENHD_FL_UP a bit further up in line 766?
> Can this still happen with the new allocation scheme, ie is there still a
> difference in lifetime between ->disk and ->disk->queue?
Yes, nvme_free_ns_head can s
On Sun, May 23, 2021 at 10:12:49AM +0200, Hannes Reinecke wrote:
>> +blk_set_stacking_limits(&mddev->queue->limits);
>> blk_queue_write_cache(mddev->queue, true, true);
>> /* Allow extended partitions. This makes the
>> * 'mdp' device redundant, but we can't really
>>
> Wouldn'
On Sun, May 23, 2021 at 10:10:34AM +0200, Hannes Reinecke wrote:
> Can't these conditionals be merged into a single 'if (md->disk)'?
> Eg like:
>
> if (md->disk) {
> spin_lock(&_minor_lock);
> md->disk->private_data = NULL;
> spin_unlock(&_minor_lock)
On Sun, May 23, 2021 at 09:58:48AM +0200, Hannes Reinecke wrote:
>> +/*
>> + * This is so fdisk will align partitions on 4k, because of
>> + * direct_access API needing 4k alignment, returning a PFN
>> + * (This is only a problem on very small devices <= 4M,
>> + * otherwise fd
On Fri, May 21, 2021 at 05:44:07PM +, Luis Chamberlain wrote:
> Its not obvious to me why using this new API requires you then to
> set minors explicitly to 1, and yet here underneath we see the minors
> argument passed is 0.
>
> Nor is it clear from the documentation.
Basically for all new d
On Sun, May 23, 2021 at 09:46:01AM +0200, Hannes Reinecke wrote:
> ... and also fixes an issue with GENHD_FL_UP remained set in an error path
> in __device_add_disk().
Well, the error path in __device_add_disk is a complete disaster right
now, but Luis is looking into it fortunately.
On Fri, May 21, 2021 at 05:16:46PM +, Luis Chamberlain wrote:
> > - /* in consecutive minor range? */
> > - if (bdev->bd_partno < disk->minors) {
> > - *devt = MKDEV(disk->major, disk->first_minor + bdev->bd_partno);
> > - return 0;
> > - }
> > -
>
> It is not obvious
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